Multi-processor computer system with transactional memory

Details Multi-processor computer system with transactional memory Multi-processor computer system with transactional memory

2005-04-12

2005-04-12

Robertson, David L. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

06880045

ABSTRACT:
A cache coherent distributed shared memory multi-processor computer system is provided which supports transactional memory semantics. A cache flushing engine and temporary buffer allow selective forced write-backs of dirty cache lines to the home memory. A flush can be performed from the updated cache to the temporary buffer and then to the home memory after confirmation of receipt or from the updated cache to the home memory directly with the temporary buffer holding the old data until confirmation that the home memory contains the update.

REFERENCES:
patent: 5892970 (1999-04-01), Hagersten
patent: 5961623 (1999-10-01), James et al.

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