Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-06-08
2004-06-01
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S133000, C711S147000, C711S136000, C711S142000, C711S141000, C710S200000
Reexamination Certificate
active
06745294
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to multi-processor computer systems and more particularly to cache-coherent systems.
BACKGROUND ART
High performance, multi-processor computer systems with a large number of microprocessors are built by interconnecting a number of node structures, each node containing a subset of the processors and memory in the system. While the memory in the system is distributed, several of these systems support a shared memory abstraction where all the memory in the system appears as a large memory common to all processors in the system. To support high-performance, these systems typically allow processors to maintain copies of portions of memory data in their local caches where the data is most quickly available. However, for safety, it is desirable, after caching new data, to send the new data down to the memory in the system because it is a safer environment with a large range of tools for recovering any lost data.
Since multiple processors can cache the same data, these systems must incorporate a cache coherence mechanism to keep the copies coherent, or up-to-date.
In some cache-coherent systems, each memory block (typically a portion of memory tens of bytes in size) is assigned a “home node”, which maintains all necessary global information for that memory block, manages the sharing of that memory block, and guarantees its coherence. The home node maintains a directory, which identifies the nodes that possess a copy of the memory block. When a node processor requires a copy of the memory block, it requests the memory block from its local cache. If the data is found, the memory access is to the local cache. Alternatively, if the data is not found, a remote memory access may be performed to the home node. The home node supplies the data from memory if its memory has the latest data. If another node has the latest copy of the data, the home node directs this node to forward the data to the requesting node. The data is then stored in the local cache of the requesting node or returned to the home memory and then sent to the requesting node.
In cache-coherent systems, multiple copies of the same memory block can exist in different nodes. These copies must be read-only and are called “clean” copies in a “shared” state.
When a processor updates its local cache copy, it must ensure that all other copies are invalidated. The processor sends a request to the home memory for the memory block to be owned only by that processor. In response, other processors, which have clean, shared copies of the memory block in their caches, must be sent a memory block recall command.
In current systems, once all processors have responded that the memory block is no longer contained in their caches, the home memory sends a message back to the updating processor that it is now the sole “owner” of the memory block. Consequently, the processor has an “exclusive” and “modified” data copy, which holds the most recent value of the data. The other copies of the memory block are invalid and the copy in the home memory is “stale”.
A System Control Unit (SCU) provides the control and the path for data transactions among the following sources and destinations within the node: the processors within the node; the local (node) portion of the memory system; the network connecting all of the nodes of the multi-processor computer system; and the input/output (I/O) system of the local node.
A serious problem in the state-of-art cache-coherent shared-memory multiprocessor system designs is that the memory copy is stale after the crash of the owner node. In other words, the most recent value of a memory block is lost when the cache content is irretrievable at a failed owner node.
In many situations, the software may demand a selective cache-flushing scheme in order to define a synchronization point, at which the most recent value of a memory block is reflected at the home memory by flushing the owner cache.
In today's processor designs, cache flushing is normally implemented as an expensive flushing operation, which may result in wiping out the entire cache rather than the desired cache blocks alone. This flushing of the entire cache of a node is problematic in that it takes considerable computer time to restore a cache. Some systems try to flush a single line of the caches to obtain faster operation, but specific hardware is required and only the operating system can access the hardware so the faster operation is costly. Also although some processors provide selective cache-flushing instructions, there are no guarantees of the correctness unless the cache-flushing instruction has system-wide semantics, which is extremely expensive.
Thus, a system has been long sought and long eluded those skilled in the art, which would provide an efficient implementation of transactional memory and be transparent to the application programs.
DISCLOSURE OF THE INVENTION
The present invention provides a method for cache flushing in a computer system having a processor, a cache, a synchronization primitive detector, and a cache flush engine. The method includes providing a synchronization primitive from the processor into the computer system; detecting the synchronization primitive in the synchronization primitive detector; providing a trigger signal from the synchronization primitive detector in response to detection of the synchronization primitive; providing cache information from the cache flushing engine into the computer system in response to the trigger signal; and flushing the cache in response to the cache information in the computer system. This results in improved fault tolerance and system performance.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4958273 (1990-09-01), Anderson et al.
patent: 5669002 (1997-09-01), Buch
patent: 5724549 (1998-03-01), Selgas et al.
patent: 5745730 (1998-04-01), Nozue et al.
U.S. patent application Ser. No. 09/877,368, Wilson et al., filed Jun. 8, 2001.
U.S. patent application Ser. No. 09/258,549, Pong, filed Feb. 28, 1999.
Nguyen Tung
Pong Fong
Russell Lance
Wilson Kenneth Mark
Xu Lu
Hewlett--Packard Development Company, L.P.
Kim Matthew
Li Zhuo H.
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