Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-10-10
2006-10-10
Kim, Matthew (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S119000, C711S130000, C711S135000, C711S137000, C711S141000, C711S142000, C711S143000, C711S147000, C711S148000
Reexamination Certificate
active
07120752
ABSTRACT:
A cache coherent distributed shared memory multi-processor computer system is provided with a memory controller which includes a recall unit. The recall unit allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the recall unit, a recall (“flush”) command is issued which forces the owner cache to write-back the dirty cache line to be flushed. The memory controller will inform the recall unit as each recall operation is completed. The recall unit operation will be interrupted when all flush requests are completed.
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Nguyen Tung
Pong Fong
Russell Lance
Wilson Kenneth Mark
Xu Lu
Hewlett--Packard Development Company, L.P.
Kim Matthew
Lange Richard P.
Li Zhuo H.
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