Multi-processor circuit with shared memory banks

Details Multi-processor circuit with shared memory banks Multi-processor circuit with shared memory banks

2006-12-13

2011-12-06

Thomas, Shane M (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S165000, C711SE12084, C711SE12002

Reexamination Certificate

active

08074031

ABSTRACT:
A plurality of processors in a multiprocessor circuit is electrically connected to a plurality of independently addressable memory banks via a connection circuit. The connection circuit is arranged to forward addresses from a combination of the processors to addressing inputs of memory banks selected by the addresses. The connection circuit provides for a conflict resolution scheme wherein at least one of the processors is associated with one of the memory banks as an associated processor. The connection circuit guarantees the associated processor a higher minimum guaranteed access frequency to the associated memory banks than to non-associated memory banks. A defragmenter detects data associated with a task running on the associated processor that is stored on one of the memory banks and moves the data to the associated memory banks during execution of the task.

REFERENCES:
patent: 6226726 (2001-05-01), Kermani et al.
patent: 6965974 (2005-11-01), Bays et al.
patent: 2005/0132140 (2005-06-01), Burger et al.
patent: 03/085524 (2003-10-01), None

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