Electrical computers and digital data processing systems: input/ – Intrasystem connection
Reexamination Certificate
2001-05-08
2004-06-29
Vo, Tim (Department: 2189)
Electrical computers and digital data processing systems: input/
Intrasystem connection
C709S215000, C711S150000
Reexamination Certificate
active
06757761
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates to the fields of multi-processor architectures and arrangements suitable for distributed and parallel processing of data such as signal and image processing.
CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
FEDERALLY SPONSORED RESEARCH AND DEVELOPMENT STATEMENT
This invention was not developed in conjunction with any Federally sponsored contract.
BACKGROUND OF THE INVENTION
There are many applications of image and signal processing which require more microprocessing bandwidth than is available in a single processor at any given time. As microprocessors are improved and their operating speeds increase, so too are the application demands continuing to meet or exceed the ability of a single processor. For example, there are certain size, weight and power requirements to be met by processor modules or cards which are deployed in military, medical and commercial end-use applications, such as a line replaceable unit (LRU) for use in a signal processing system onboard a military aircraft. These requirements typically limit a module or card to a maximum number of microprocessors and support circuits which may be incorporated onto the module due to the power consumption and physical packaging dimensions of the available microprocessors and their support circuits (memories, power regulators, bus interfaces, etc.).
As such, a given module design or configuration with a given number of processors operating at a certain execution speed will determine the total bandwidth and processing capability of the module for parallel and distributed processing applications such as image or signal processing. Thus, as a matter of practicality, it is determined whether a particular application can be ported to a specific module based upon these parameters. Any applications which cannot be successfully be ported to the module, usually due to requiring a higher processing bandwidth level than available on the module, are implemented elsewhere such as on mini-super computers.
As processor execution rates are increased, microprocessing system component integration is improved, and memory densities are improved, each successive multi-processor module is redesigned to incorporate a similar number of improved processors and support circuits. So, for example, a doubling of a processor speed may lead to the doubling of the processing bandwidth available on a particular module. This typically allows twice as many “copies” or instances of applications to be run on the new module than were previously executable by the older, lower bandwidth module. Further, the increase in processing bandwidth may allow a single module to run applications which were previously too demanding to be handled by a single, lower bandwidth module.
The architectural challenges of maximizing processor utilization, communication and organization on a multi-processor module remains constant, even though processor and their associated circuits and devices tend to increase in capability dramatically from year to year.
For many years, this led the military to design specialized multi-processor modules which were optimized for a particular application or class of applications, such as radar signal processing, infrared sensor image processing, or communications signal decoding. A module designed for one class of applications, such as a radar signal processing module, may not be suitable for use in another application, such as signal decoding, due to architecture optimizations for the one application which are detrimental to other applications.
In recent years, the military has adopted an approach of specifying and purchasing computing modules and platforms which are more general purpose in nature and useful for a wider array of applications in order to reduce the number of unique units being purchased. Under this approach, known as “Commercial-Off-The-Shelf” (COTS), the military may specify certain software applications to be developed or ported to these common module designs, thereby reducing their lifecycle costs of ownership of the module.
This has given rise to a new market within the military hardware suppliers industry, causing competition to develop and offer improved generalized multi-processor architectures which are capable of hosting a wide range of software applications. In order to develop an effective general hardware architecture for a multi-processor board for multiple applications, one first examines the common needs or nature of the array of applications. Most of these types of applications work on two-dimensional data. For example, in one application, the source data may represent a 2-D radar image, and in another application, it may represent 2-D magnetic resonance imaging. Thus, it is common to break the data set into portions for processing by each microprocessor. Take an image which is represented by an array of data consisting of 128 rows and 128 columns of samples. When a feature recognition application is ported to a quad processor module, each processor may be first assigned to process 32 rows of data, and then to process 32 columns of data. In signal processing parlance this is known as “corner turning”. Comer turning is a characteristic of many algorithms and applications, and therefore is a common issue to be addressed in the interprocessor communications and memory arrangements for multi-processor boards and modules.
One microprocessor which has found widespread acceptance in the COTS market is the Motorola PowerPC [TM]. Available modules may contain one, two, or even four PowerPC processors and support circuits. The four-processor modules, or “quad PowerPC” modules, are of particular interest to many military clients as they represent a maximum processing bandwidth capability in a single module. There are three fundamentally different quad Power PC board or module architectures on the market, which are are illustrated in
FIGS. 1 through 3
.
FIG. 1
illustrates an architecture known as the “distributed memory architecture”, while both
FIGS. 2 and 3
represent “dual memory” architectures. These architectures, though, could be employed well with other types and models of processors, inheriting the strengths and weaknesses of each architecture somewhat independently of the processor chosen for the module.
One advantage of distributed memory architectures as shown in
FIG. 1
is that input data received at a central crossbar (
15
) can be “farmed out” via local crossbars (
100
and
101
) to multiple processors “cores” (
16
,
17
,
18
and
19
) that perform the processing of the data in parallel and simultaneously. Quad PowerPC cards such as this are offered by companies such as CSP Inc., Mercury Computer Systems Inc., and Sky Computers Inc.
For example, during the first phase of processing a hypothetical two-dimensional (2-D) data set of 128 rows by 128 columns shown in TABLE 1 on a distributed memory dual processor card, a first set of 32 rows (rows 0-31) of data may be sent to a first processor core (
16
), a second set of 32 rows (rows 32-63) of data would be sent to a second processor core (
17
), a third set of 32 rows (rows 64 to 95) of data to the third processor core (
18
), and the fourth set of 32 rows (rows 96 to 127) of data to the fourth processor core (
19
). Then, in preparation for a second phase of processing data by columns, a corner turning operation is performed in which the first processor core would receive data for the first 32 columns, the second processor core would receive the data for the second 32 columns, and so forth.
TABLE 1
Example 128 × 128 Data Array
Column
Row
0
1
2
3
4
. . .
126
127
0
0XFE
0x19
0x46
0x72
0x7A
. . .
0x9C
0x4B
1
0x91
0x22
0x4A
0xA4
0xF2
. . .
0xBE
0xB3
2
0x9A
0x9C
0x9A
0x98
0x97
. . .
0x43
0x44
4
0x00
0x00
0x81
0x8F
0x8F
. . .
0x23
0x44
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
126
0x34
0x3A
0x36
0x35
0x45
. . .
0xFB
0xFA
127
0x75
0x87
0x99
0xF0
0xFE
. . .
0xFF
0xFA
Regardless of the type of bus used to interconnect the processor cores, high speed parallel or serial, this ar
Bartlett James R.
Labhart Jay T.
Smith Winthrop W.
Frantz Robert H.
Tera Force Technology Corp.
Vo Tim
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