Multi-processing memory duplication system

Details Multi-processing memory duplication system Multi-processing memory duplication system

2006-05-16

2006-05-16

Perveen, Rehana (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S314000, C711S141000, C714S001000

Reexamination Certificate

active

07047341

ABSTRACT:
Embodiments of the present invention relate to an apparatus including a first processor module, a second processor module, and a bus. The bus is coupled to the first processor module and the second processor module. The bus is configured to transmit both processor related communication and memory related communication. In embodiments, the first processor module includes a first central processing unit and the second processing module includes a second central processing unit. Accordingly, in embodiments of the present invention, a single bus can be used to communicate between processors and memories. The present invention is useful for real time duplication of memory, high speed duplication of memory, and/or a coherency check of memory between a first processing module and a second processing module.

REFERENCES:
patent: 3889237 (1975-06-01), Alferness et al.
patent: 4654819 (1987-03-01), Stiffler et al.
patent: 4905145 (1990-02-01), Sauber
patent: 4941087 (1990-07-01), Kap
patent: 5157663 (1992-10-01), Major et al.
patent: 5214652 (1993-05-01), Sutton
patent: 5235700 (1993-08-01), Alaiwan et al.
patent: 5278975 (1994-01-01), Ishihata et al.
patent: 5325503 (1994-06-01), Stevens et al.
patent: 5394555 (1995-02-01), Hunter et al.
patent: 5473599 (1995-12-01), Li et al.
patent: 5488716 (1996-01-01), Schneider et al.
patent: 5551050 (1996-08-01), Ehlig et al.
patent: 5577204 (1996-11-01), Brewer et al.
patent: 5737514 (1998-04-01), Stiffler
patent: 5887146 (1999-03-01), Baxter et al.
patent: 5887270 (1999-03-01), Brant et al.
patent: 5907673 (1999-05-01), Hirayama et al.
patent: 5958070 (1999-09-01), Stiffler
patent: 5987621 (1999-11-01), Duso et al.
patent: 6223304 (2001-04-01), Kling et al.
patent: 6389496 (2002-05-01), Matsuda
patent: 6516442 (2003-02-01), Wang et al.
patent: 6578095 (2003-06-01), Tanaka et al.
patent: 6631474 (2003-10-01), Cai et al.
patent: 6647508 (2003-11-01), Zalewski et al.
patent: 6742072 (2004-05-01), Prakash et al.
patent: 6772298 (2004-08-01), Khare et al.
patent: 6823429 (2004-11-01), Olnowich
patent: 2002/0145609 (2002-10-01), Emmot et al.
PCIMG, “CompactPCI”, PCIMG, http://ww.picmg.org/test/compci.htm.
PCIMG, “CompactPCI Short Form Specification”, 1995, PCIMG.
IEEE, “IEEE Standard for Scalable Coherent Interface (SCI)”, 1992, IEEE, pp. iii-vi.
Jon Crowcroft, “Open Distributed Systems”, 1996, University Colledge London, http://www.cs.ucl.ac.uk/staff/jon/ods.
Jan Lindstrom, “HIgh Availability and Fault-Tolerance in Real-Time Databases”, 2001, The Computer Science Department at the University of Helsinki, http://www.cs.helsinki.fi/u/kraatika/courses/sem01a/lindstrom.pdf.
PCI Special Interest Group, “PCI-to-PCI Bridge Architecture Specification”, 1998, PCI Special Interest Group, Rev. 1.1, pp. 11-13 and 19-30.

Affiliated with

Also associated with

Rating

Multi-processing memory duplication system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-processing memory duplication system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-processing memory duplication system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3547598