Multi-ported SRAM cell with shared bit and word lines and...

Details Multi-ported SRAM cell with shared bit and word lines and... Multi-ported SRAM cell with shared bit and word lines and...

2001-10-31

2002-10-29

Le, Vu A. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S154000

Reexamination Certificate

active

06473334

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a memory element that stores data as part of a memory cache, register file, or other memory array. More particularly, the present invention relates to a static random access memory (SRAM) element that is implemented with a plurality of ports, which can simultaneously access the memory element.
2. Background of the Invention
Memory devices store and retrieve large quantities of digital data. Memory capacities in digital systems are commonly expressed in terms of bits (binary digits), since a separate storage element is used to store each bit of data. Each storage element is referred to as a cell. Memory capacities are also sometimes quantified in terms of bytes (8 or 9 bits) or words (which may be arbitrarily defined, but commonly comprises 16 or more bits). Every bit, byte, or word is stored in a particular location, identified by a unique numeric address. Typically, one or more bytes of data is stored or retrieved during each cycle of a memory operation.
The performance of computer systems has continued to increase at a remarkable rate, while the cost has decreased just as dramatically. Part of the reason for this increased performance with decreased cost is attributable to the dramatic reduction in the cost of memory elements, while the speed and performance has increased. Current memory devices are smaller, operate at a higher speed, consume less power, and operate more reliably than the memory products that were on the market only a few years ago.
The most flexible digital memories are those that allow for data storage (or writing) as well as data retrieval (reading). Memories in which both of these functions can be rapidly and easily performed, and whose cells can be accessed in random order (independent of their physical locations), are referred to as random-access memories (RAMs). Read-only memories (ROMs) are those in which only the read operation can be performed rapidly. Entering data into a ROM is referred to as programming the ROM. This operation is much slower than the writing operation used in RAMs.
The storage cells in a typical semiconductor memory are arranged in an array consisting of horizontal rows and vertical columns. Each cell shares electrical connections with all the other cells in its row or column. The horizontal lines (which enable reading and writing operations) connect to all the cells in the row and are called word lines. The vertical lines (along which data flows into and out of the cells) are referred to as bit lines. Each cell therefore has a unique memory location, or address, which can be accessed at random through the selection of the appropriate word and bit line. Some memories are designed so that all the cells in a row are accessed simultaneously. This array configuration of semiconductor memories lends itself well to the regular structured designs that are favored in very large scale integrated circuits.
In semiconductor RAMs, information is stored in each cell either through the charging or discharging of a capacitor or the setting of the state of a bi-stable latch circuit. With either method, the information on the cell is destroyed if the power is interrupted. Such memories are therefore referred to as volatile memories. When the charge on a capacitor is used to store data in a semiconductor-RAM cell, the charge needs to be periodically refreshed, since leakage currents will remove it in a few milliseconds. Hence, volatile memories based on this storage mechanism are known as dynamic RAMs, or DRAMs. If the data is stored (written) by setting the state of a latch, it will be retained as long as power is connected to the cell (and latch is not overwritten by another write signal). RAMs fabricated with such cells are known as static RAMs, or SRAMs. Unlike DRAM cells, there is no need to refresh the cell to maintain the state of the cell.
One of the important criteria is that the memory cell does not lose its data (or change state) during a read operation. Thus, the memory cell must be stable under all normal reading conditions to ensure proper operation. At the same time, the memory cell must be writable to permit the contents of the cell to be modified when instructed by the system. In addition, the memory cell must have noise margins that are reasonable so that the memory cell holds its state even in the event that noise is present on the word lines or bit lines.
In some designs, it is desirable to have more than one read operation at a time. A dual ported memory array can support two simultaneous read operations, either from the same cell or from two cells in the same array. One cell of a conventional dual-ported SRAM array is shown in
FIG. 1
for purposes of illustration. The memory array would include a plurality of memory cells constructed in much the same fashion. With a multi-ported SRAM cell, the ability to maintain the memory state of the cell during simultaneous read operations on the different ports becomes more difficult to achieve because current drawn through the access transistors increase the voltage on the “0” side of the latch. If not properly designed, a read operation from multiple ports could “disturb” the state of the memory cell. As shown in
FIG. 1
, the memory cell
5
is comprised of a pair of latches (shown as inverters
10
,
15
) that store or hold the data. The inverters
10
,
15
work in conjunction to store a data bit value. If the output of inverter
10
is a low voltage state (i.e., a “0”), then the output of inverter
15
will be a high voltage state (i.e., a “1”). Consequently, each side of the memory cell
5
is maintained at a different logical value. The state of these logical values determines whether the memory cell is storing a “0” or a “1”. For example, if the output of inverter
10
is a “1”, and the output of inverter
15
is a “0”, this may represent a “1” in the memory cell
5
. Conversely, if the output of inverter
10
is a “0”, and the output of inverter
15
is a “1”, this may represent a “0” in the memory cell
5
. Although only one memory cell is shown in
FIG. 1
, one skilled in the art will understand that multiple memory cells are configured horizontally and vertically in a two dimensional array.
Typically, a word line accesses each memory cell in a particular horizontal row.
FIG. 1
shows a dual-ported SRAM cell, and thus two word lines access each memory cell in a horizontal row. In
FIG. 1
, these word lines are represented as wordline
1
and wordline
2
. To read data from port
1
, wordline
1
is asserted, thus turning on access transistors
12
,
14
, and thereby enabling the state of inverters
10
,
15
to be read by associated port
1
bit lines. Conversely, to read data from port
2
, wordline
2
is asserted, turning on access transistors
16
,
18
, and thereby enabling the associated port 2 bit lines to read the state of the memory cell
5
.
Data is read from the memory cell
5
on two complementary bitlines, which typically are shown as extending vertically in a memory diagram. In accordance with this convention,
FIG. 1
shows a low bit line and a high bit line connected to each memory cell. Thus, for example, bitline_L(
1
) and bitline_H(
1
) are used to access data in conjunction with wordline
1
. When wordline
1
is asserted, the access transistor gates
12
,
14
(shown as field effect transistors, or FETs) turn-on, permitting the state of inverter
10
to be read on bitline_H(
1
), and the state of inverter
15
to be read on bitline_L(
1
). If bitline_H(
1
) goes high, and bitline_L(
1
) goes low, this signals that the state of memory cell is a “1” (although a different convention could be used, if desired). Conversely, if bitline_H(
1
) goes low, and bitline_L(
1
) goes high, this signals that the state of memory cell is a “0”. The voltage levels of bitline_L(
1
) and bitline_H(
1
) are compared in a sense amp (not shown)

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