Multi-ported memory architecture using single-ported RAM

Details Multi-ported memory architecture using single-ported RAM Multi-ported memory architecture using single-ported RAM

1997-01-17

2001-04-03

Thai, Tuan V. (Department: 2166)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S005000, C711S147000, C711S150000, C711S151000, C365S189011

Reexamination Certificate

active

06212607

ABSTRACT:

FIELD OF THE INVENTION
This invention relates in general to memory devices and in particular, to a multi-ported memory device including single-ported banks of random access memory (RAM), and means for providing orderly access through input/output ports of the multi-ported memory device to the single ported memory banks.
BACKGROUND OF THE INVENTION
Memory devices are often shared by multiple electronic devices in a computer system to reduce the number and overall costs of system components, as well as facilitate communication between the resource sharing electronic devices. Arbiter circuits are generally included in such systems to prevent collisions between multiple electronic devices simultaneously attempting to access the memory device. If the memory device is a single-port memory device, only one resource sharing device can access the memory device at a time. Therefore, arbiter circuits in systems employing such single-port memory devices, arbitrate contention by allowing only a contention winning electronic device temporary, sole access to the entire memory device. For a dual-port memory device, on the other hand, two electronic devices can concurrently read access the same location and write access different locations of the memory device, thus providing nearly twice the bandwidth of a single-port device. Access is only restricted when the electronic devices simultaneously attempt to write access the same location. Therefore, arbiter circuits in systems employing such dual-port memory devices, arbitrate contention by allowing only a contention winning electronic device temporary sole write access to the simultaneously requested location.
FIG. 1
illustrates, as an example, a block diagram of a computer system
100
including a conventional dual-port static random-access memory (SRAM)
101
with selected characteristics simplistically depicted in bubble blow-ups,
110
and
112
, for descriptive purposes, and left and right electronic devices,
105
and
106
, respectively coupled to the dual-port SRAM
101
by left and right ports,
103
and
104
. As simplistically depicted in bubble blow-up
110
, one characteristic and significant drawback of the conventional dual-port SRAM
101
is the large size of its individual memory cells (e.g.,
114
), which may be as large as eight or six transistors, for example, to accommodate its dual porting to both left and right ports,
103
and
104
, through lines
121
and
122
. Also, as simplistically depicted in bubble blow-up
112
, another characteristic and significant drawback of the conventional dual-port SRAM
101
is that its arbiter logic arbitrates at the individual memory cell level, which can add to access times.
It is a goal of integrated circuit design to minimize the die size and consequently, the cost of an integrated circuit device. Another goal is to maximize the performance of the integrated circuit device. Both of these goals are ongoing and especially important in designing high density memory devices for advanced computer systems.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a shared resource memory device of minimized die size.
Another object is to provide a shared resource memory device having faster read and write access times than conventional dual-port memory devices, while providing the same or higher bandwidth.
Still another object is to provide a shared resource memory device which minimizes the required interface control activities of electronic devices sharing the shared resource memory device.
These and additional objects are accomplished by the various aspects of the present invention, wherein briefly stated, one aspect is a multi-ported memory device having at least two input/output ports, comprising: a plurality of single-ported memory banks individually having a plurality of addressable memory cells; means for receiving bank access request signals through the at least two input/output ports for selected ones of the plurality of single-ported memory banks, and granting exclusive access through individual ones of the at least two input/output ports to individual ones of the selected single-ported memory banks on a first received access request basis; and at least one first mail-box register dedicated to storing data received through a first one of the at least two input/output ports, and transmitted through a second one of the at least two input/output ports.
In another aspect, a multi-ported memory device having at least two input/output ports, comprises: an array of individually addressable memory cells organized into single-ported memory banks; means for reserving selected ones of the single-ported memory banks for exclusive communication through individual ones of the at least two input/output ports until released; and means for coupling the reserved single-ported memory banks to the individual ones of the at least two input/output ports upon addressing of memory cells of the reserved single-ported memory banks.
In still another aspect, a multi-ported memory device having at least two input/output ports, comprises: a plurality of single-ported memory banks individually having a plurality of addressable memory cells; a plurality of mail-box registers individually dedicated to storing data received through a corresponding one of the at least two input/output ports, and transmitted through another corresponding one of the at least two input/output ports; and means for providing access during a first mode of operation to selected ones of the plurality of single-ported memory banks such that access is provided through only one of the input/output ports at a time, and providing access at all times during a second mode of operation to the plurality of mail-box registers through corresponding ones of the input/output ports.
Additional objects, features and advantages of the various aspects of the present invention will become apparent from the following description of its preferred embodiments, which description should be taken in conjunction with the accompanying drawings.


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Article entitled: “QS75836 High-Speed CMOS 8K×36 Block-Allocated Shared-Port RAM with Flexi-Burst,”Quality Semiconductor, Inc., (MDSF-00011-08) pps. 1-18 (Jan. 9, 1996).

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