Multi-ported and interleaved cache memory supporting multiple si

Details Multi-ported and interleaved cache memory supporting multiple si Multi-ported and interleaved cache memory supporting multiple si

1996-12-16

1999-07-13

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711129, 36523003, G06R 1200

Patent

active

059241179

ABSTRACT:
A high speed pseudo-, 8-, 16-, or greater, ported cache memory, and associated effective address generation scheme. Based upon either two-port building blocks, or twice as many single-port building blocks, which are interleaved, the cache memory is arranged as a functional equivalent to a true 8-, 16-, or greater ported interleaved cache memory.

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