Multi-port SRAM core array

Details Multi-port SRAM core array Multi-port SRAM core array

1995-11-30

1996-10-01

Nelms, David C.

Static information storage and retrieval

Addressing

Multiple port access

36523008, 36518901, 36518905, G11C 800

Patent

active

055616380

ABSTRACT:
A multi-port SRAM (static random access memory) core array has a core cell with a single-ended, pseudo-differential write access port and differential, indirect access read ports. The architecture of the features of the multi-port SRAM core array allows direct scaling of the number of write and read access ports to any practical limit with no adverse effects on cell stability margins and therefore data integrity.

REFERENCES:
patent: 4958322 (1990-09-01), Kosugi et al.
patent: 5345425 (1994-09-01), Shikatani
patent: 5473574 (1995-12-01), Clemen et al.
"A 180-MHz 0.8-um BiCMOS Modular Memory Family of DRAM and Multiport SRAM", Silburt et al, IEEE Journal of Solid-State Circuits, vol. 28, No. 3, Mar. 1993.
"A 2.2 W, MHz Superscalar RISC Microprocessor", Gerosa et al, IEEE Journal of Solid-State Circuits, vol. 29, No. 12, Dec. 1994.

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