Multi-port SRAM access control using time division multiplexed a

Details Multi-port SRAM access control using time division multiplexed a Multi-port SRAM access control using time division multiplexed a

1997-10-29

2000-03-07

Auve, Glenn A.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

709249, G06F 1300

Patent

active

060353600

ABSTRACT:
A memory interface for multi-port access to a memory unit, such as a static random-access memory (SRAM) device. The memory interface, which is generally adapted for a local area network (LAN) forwarding engine, provides single port read/write access to SRAM device, and arbitrates requests from the access interfaces to allocate bandwidth of the SRAM device among the requests. One embodiment allocates at least 50% of the bandwidth to a peripheral component interface (PCI) bus target interface and a PCI bus master interface, collectively. The arbitration logic may include a plurality of bandwidth control registers associated with respective access interfaces used to determine a permitted amount of bandwidth that an access interface is to have, wherein a request from an access interface is masked based on a value in its associated bandwidth control register. Arbitration can further allocate bandwidth using time division multiplexing.

REFERENCES:
patent: 4933846 (1990-06-01), Humphrey et al.
patent: 5471639 (1995-11-01), Harrington
patent: 5548587 (1996-08-01), Bailey et al.
patent: 5557783 (1996-09-01), Oktay et al.

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