Static information storage and retrieval – Addressing – Multiple port access
Reexamination Certificate
2000-03-14
2001-05-15
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Multiple port access
C365S069000, C365S156000
Reexamination Certificate
active
06233197
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor memories and memory compilers. In particular, the present invention relates to a memory and memory compiler in which selected bit line pairs are crossed at multiple locations to compensate for coupling capacitance with adjacent bit lines.
In high density semiconductor memories, coupling capacitance between adjacent bit lines in the memory can corrupt the data that is written to or read from the memory. Two methods of avoiding the effects of coupling capacitance include providing extra spacing between the bit lines and shielding one bit line from the next bit line with power and ground conductors during layout of the memory. However, these methods are costly in terms of silicon area for high density memories. Moreover, even with proper spacing, it is often difficult to completely eliminate capacitive coupling.
U.S. Pat. No. 5,140,556 to Cho et al. discloses a single-port dynamic random access memory (DRAM) circuit having dummy cells, which are connected to twisted bit lines. The memory is divided into four equal segments, and the bit lines of adjacent memory cells are twisted between the segments to compensate for capacitive coupling. However, this patent does not address avoidance of coupling capacitance between bit lines of two or more ports, which are part of the same memory cell, in a multi-port memory. In addition, while this implementation can be used with custom memory devices, it is difficult, if not impossible, to implement this method in a memory compiler for embedded memory devices in which the number of rows in the memory is variable.
A method of compensating for coupling capacitance between bit lines of different ports of the same memory cell has been used by LSI Logic Corporation in their embedded memory cores. With multi-port memories, capacitive coupling can occur between the bit lines of different ports during simultaneous access (writing or reading) of different cells of the same column of the memory. With an LSI dual-port memory core, the internal bit lines (BLA and BLAN) of one of the two ports were switched (i.e. crossed) at the middle of each column of the memory. By crossing the internal bit lines of one port at the middle of the memory, the effects of capacitive coupling along the upper half of the memory is cancelled out by the capacitive coupling along the lower half of the memory.
Since the bit lines of one port were switched in the middle of the memory for one port, the data inputs and data outputs of that port were inverted when writing to or reading from the upper half of the memory, which saw an inversion in the crossed bit lines at the middle of the memory. This ensured that the same data could be written to and read from the upper half of the memory through the port with switched bit lines and through the port without switched bit lines.
Unfortunately, the above method of compensating for coupling capacitance has some inherent difficulties. In memory compiler applications, where the number of rows in the memory is variable, it is very difficult for the compiler algorithm to locate the bit line crossing location exactly in the middle of each column. Also, the row address bits, which identify whether the upper or lower half of the memory is being accessed, had to be decoded to determine whether the data inputs or data outputs had to be inverted for the port having the switched bit lines. This decoding can be very tedious and can become very difficult to implement in a memory compiler environment where the number of physical rows can vary.
To optimize the address decoding logic, the memory compiler algorithm is written to find a tolerance capacitance below which coupling between adjacent bit lines has no significant effect. This tolerance capacitance is then correlated to a maximum number of physical rows along which there is no compensation. The total memory array is then divided into two parts such that the maximum difference between the two parts is less than or equal to the tolerance size. Keeping this criterion in mind, the algorithm chooses a switch point to optimize the address decoding.
Although this algorithm reduces complexity of the address decoding somewhat, it is difficult for the memory compiler algorithm to find a good and reliable tolerance capacitance since the tolerance capacitance can vary significantly with process variation, amount of circuit noise and power bumps. The chances of silicon failure using the above-technique can be very high in some applications.
Improved structures and methods of compensating for coupling capacitance between adjacent bit lines in large multi-port memories are desired.
SUMMARY OF THE INVENTION
One aspect of the present invention is directed to a multi-port semiconductor memory, which includes first and second data ports and a plurality of memory cells arranged in rows and columns. Each column comprises first and second pairs of complementary bit lines, which are coupled to each of the memory cells in that column. The first pair of bit lines cross one another between every N and N+1 of the memory cells the column, where N=2
M
and M is an integer variable greater than zero. The memory further includes a plurality of row address input bits for each of the first and second ports, which have a least significant row address bit and which address the plurality of memory cells. A data inversion circuit is coupled between the first pair of bit lines and the first data port, which selectively inverts the first pair of bit lines as a function of the first port's (M+1)th row address input bit only, as measured from the least significant row address input bit.
Another aspect of the present invention is directed to a multi-port semiconductor memory, which includes first and second data ports and a plurality of memory core cells arranged in a plurality of rows and a plurality of columns. Each of the columns includes first and second pairs of complementary bit lines, which are coupled to the memory cells that are located in that column. A wordline decoder circuit addresses the plurality of memory core cells and has a plurality of row address input bits, including a least significant row address bit, for each of the first and second data ports. The memory further includes a circuit for crossing the first pair of bit lines between every N and N+1 of the memory core cells in each of the columns, where N=2
M
and M is an integer variable greater than zero. A data inversion circuit selectively inverts the first pair of bit lines between each column and the first data port as a function of only the (M+1)th row address bit for the first port, as measured from the least significant row address bit.
Yet another aspect of the present invention is directed to a computer readable medium, which includes a semiconductor memory compiler. The memory compiler has instructions which, when executed by a computer cause the computer to perform steps of: tiling a plurality of memory core cells in a plurality of rows and columns to form a memory layout pattern having first and second data ports, wherein each of the columns comprises first and second pairs of complementary bit lines, which are coupled to the memory cells that are located in that column; placing a wordline decoder circuit within the memory layout pattern, which comprises a plurality of row address input bits, including a least significant row address bit, for each of the first and second data ports, which address the plurality of memory cells; crossing the first pair of bit lines between every N and N+1 of the memory core cells in each of the columns, where N=2
M
and M is an integer variable greater than zero; and placing a selective data inversion circuit in the memory layout pattern between the first pair of bit lines and the first data port, for selectively inverting the first pair of bit lines as a function of only the (M+1)th row address bit for the first port, as measured from the least significant row address bit.
REFERENCES:
paten
Agrawal Ghasi R.
Wik Thomas R.
Lam David
LSI Logic Corporation
Nelms David
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