Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Patent
1995-03-30
1998-09-22
Gossage, Glenn
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
711149, 711157, 711393, G06F 1200, G06F 1300
Patent
active
058130373
ABSTRACT:
A multi-port register file suitable for use in a reservation station in a superscalar microprocessor. The multi-port register is a static random access memory (SRAM) array which interleaves the data bits of the reservation station entries in a pair of storage cells. Because data may be associatively written to multiple entries within the SRAM cell array, a capacitance isolation mechanism including a plurality of inverters may be provided in data lines, such as writeback data lines, of the array. The isolation mechanism is situated so as to be shared by two interleaved cells within the SRAM array. The storage cells within the reservation station register may include at least one read port and a plurality of write or writeback ports coupled to a plurality of read enable and write enable lines. In one embodiment, cells of the SRAM array are exclusively read and thus a reduced sized sampling transistor may be used for the read ports. Power saving techniques are described for reducing the power consumption of the reservation station SRAM array which include delaying the activation of write enable lines and a preference for reading low power states to prevent the need for excessive precharging of bit lines of the SRAM array.
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Henstrom Alexander P.
Martell Robert W.
Gossage Glenn
Intel Corporation
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