Multi-port random access memory

Details Multi-port random access memory Multi-port random access memory

1997-07-24

2001-09-11

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Multiple port access

C365S201000, C365S154000, C365S189040

Reexamination Certificate

active

06288969

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a multi-port RAM (random access memory) which enhances a shadow write test function.
BACKGROUND ART
Well known are RAMs which have at least one address port and include storage elements (core cells). In a paper by A. L. Silburt et al entitled “A 180-MHz 0.8-&mgr;m BiCMOS Modular Memory Family of DRAM and Multiport SRAM”, IEEE Journal of Solid-State Circuits, Vol. 28, No. 3, March 1993, p. 222, at 227 shows various arrays of RAM storage elements.
In RAMs, a problem is to develop a practical, non-intrusive method for sensitizing shorts between bit lines from different ports. In a paper by B. Nadeau-Dostie et al entitled “Serial Interfacing for Embedded-Memory Testing”, IEEE Design & Test of Computers, April 1990, p. 52 discloses BIST (built-in self test) architecture and memory test.
Detection of shorts due to manufacturing defects between bit lines from different ports which run parallel to each other over large distances (the “height” of the memory array) is difficult due to the small differential signal swing used in high-speed memory port architectures. Shorts between word lines from different ports are likewise difficult to detect without special test algorithms. Such faults may pass undetected by conventional BIST or functional testing means during manufacturing test and result in intermittent failures in the field. A shadow write methodology may be used to sensitize the port-to-port bit line and word line short failures during BIST or functional testing.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved multi-port RAM.
In accordance with one aspect of the present invention, there is provided a multi-port RAM (random access memory) comprising RAM cells of m rows by n columns, each RAM cell including storage means for storing differential binary data, the RAM cells of each column being commonly coupled to a respective set of M data paths, m, n and M being integers, the multi-port RAM further comprising: access means for conducting data access to the RAM cells via the data paths; and path select means for determining data paths so that data accessing is enabled via the selected data paths and data accessing is disabled via the non-selected data paths.
In an example, the access means comprises data read means for reading differential binary data stored in the storage means via the selected data path during a read mode. The binary data stored in the storage means is read via the selected data paths and data reading is disabled via the non-selected data paths.
In an example, the access means comprises data write and read means for: (i) storing differential binary data in the storage means via the selected data path during a write mode: and (ii) reading the differential binary data stored in the storage means via the selected data path during a read mode. The binary data is read from the storage means via the selected data paths and data reading is disabled via the non-selected data paths, during the read mode.
The multi-port RAM port architectures with the path select means (shadow write) provide a practical, non-intrusive method for sensitizing shorts between bit lines and word lines from different read-only, write-only or read-write ports within a multi-port RAM. This is an innovative test enhancement feature.
With the application of the shadow write feature, bit line and word line faults between ports of a multi-port RAM may be detected during manufacturing test by standard single-port test algorithms. This allows the integration of BIST for multi-port memories using available BIST controllers developed to test single-port memories. Only minor modifications to the BIST controller are required to enable the shadow write function and allow the multi-port memory to be treated as a number of individual single-port memories.


REFERENCES:
patent: 5384734 (1995-01-01), Tsujihashi et al.
patent: 5398047 (1995-03-01), Nara et al.
patent: 5493536 (1996-02-01), Aoki
patent: 5574692 (1996-11-01), Dierke
patent: 5590087 (1996-12-01), Chung et al.
patent: 5734613 (1998-03-01), Gibson
Siburt, A.L., et al, “A 180-Mhz 0.8-um BiCMOS Modular Memory Family of DRAM and Multiport SRAM”, IEEE Journal of Solid-State Circuits, vol 28, No. 3, Mar. 1993, pp. 222-232.
Nadeau-Dostie, B., et al, “Serial Interfacing for Embedded-Memory Testing”, IEEE Design & Test of Computers, Apr. 1990, pp. 52-63.

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