Multi-port random access memory

Details Multi-port random access memory Multi-port random access memory

1996-05-09

1997-03-18

Nelms, David C.

Static information storage and retrieval

Addressing

Multiple port access

365233, 36523006, G11C 800

Patent

active

056129238

ABSTRACT:
Disclosed is a design detail for an innovative time multiplexed read port architecture implemented as part of a high-speed 9-port time slot interchange random access memory. It provides a practical, high-speed, low-power and area efficient read port structure to allow eight random access reads per clock cycle. Because all timing is internally generated from a single rising clock transition of a system clock signal, no special control or clocking is required externally to the memory.

REFERENCES:
patent: 5355335 (1994-10-01), Katsumo
patent: 5434818 (1995-07-01), Byers et al.
patent: 5473574 (1995-12-01), Clemen et al.
1985 IEEE International Solid-State Circuits Conference, SESSION III: Special Application Memories, "A 2K.times.9 Dual Port Memory", Barber et al., Feb. 1985, pp. 44-45 and 302.
1990 Symposium on VLSI Circuits, "Pipelined, Time-Sharing Access Technique for a Highly Integrated Multi-Port Memory", Tsuneo Matsumura et al, NTT LSI Laboratories, Feb. 1990, pp. 107-108.
IEEE Journal of Solid State Circuits, Endo et al. vol. 26, No. 4, Apr. 1991, "Pipelined, Time-Sharing Access Technique for an Integrated Multiport Memory", pp. 549-554.
IEEE Journal of Solid-State Circuits, vol. 28, No. 3, Mar. 1993, "A 180-MHz 0.8-.mu.m BiCMOS Modular Memory Family of DRAM and Multiport SRAM", Allan L. Silburt et al, pp. 222-232.
Fujitsu Sci. Tech. J., 24, 4, pp. 293-300 (Dec. 1988), "Self-Timed RAM: STRAM", C. Ohno.

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