Multi-port random access memory

Details Multi-port random access memory Multi-port random access memory

1996-09-18

1998-03-31

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36523005, 365200, G11C 700, G11C 800

Patent

active

057346135

ABSTRACT:
Disclosed is an architecture of a RAM (random access memory) with BIST (built-in self test) or functional test function. The RAM has a memory cell for storing differential or single-ended binary data and bit line signals are fully differential or single-ended. Shadow write is applied to read only and read-write bit lines. With the test function, port-to-port bit line shorts and port-to-port word line shorts are sensitized.

REFERENCES:
patent: 5384734 (1995-01-01), Tsujihashi
patent: 5493536 (1996-02-01), Aoki
patent: 5535159 (1996-07-01), Nii
patent: 5590087 (1996-12-01), Chung et al.
Silburt, A.L., et al, "A 180-Mhz 0.8-um BiCMOS Modular Memory Family of DRAM and Multiport SRAM", IEEE Journal of Solid-State Circuits, vol. 28, No. 3, Mar. 1993, pp. 222-232.
Nadeau-Dostie, B., et al, "Serial Interfacing for Embedded-Memory Testing", IEEE Design & Test of Computers, Apr. 1990, pp. 52-63.

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