Multi-port RAM with shadow write test enhancement

Details Multi-port RAM with shadow write test enhancement Multi-port RAM with shadow write test enhancement

1997-07-24

1999-06-15

Tran, Andrew Q.

Static information storage and retrieval

Read/write circuit

Testing

36523005, 365190, 371 212, G11C 2900

Patent

active

059128500

ABSTRACT:
A multi-port RAM (random access memory) includes RAM cells which are coupled to respective row and column lines of each port. RAM cells selected by signals on the row and column lines of a port store binary data. A ground level voltage is applied onto selected column lines in a shadow write mode. Any short between the active column lines and the column lines in shadow write will result in a significant error voltage being applied to the active column line and invalid read will result. Shorts between column lines from different ports are sensitized.

REFERENCES:
patent: 5561638 (1996-10-01), Gibson et al.
patent: 5742557 (1998-04-01), Gibbins et al.
"A 5 Gb/s 9-Port Application Specific SRAM with Built-In Self Test", Wood, S., et al, IEEE, Aug. 1995 (0-8186-7102-5/95), pp. 68-73.
"Soft-Defect Detection (SDD) Technique for a High-Reliabilty CMOS SRAM", Kuo, C., et al, IEEE Journal of Solid-State Circuits, vol. 25, No. 1, Feb. 1990, pp. 61-67.

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