Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1998-01-13
2000-12-26
Robertson, David L.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711149, 36518904, 36523005, G06F 1300
Patent
active
061674877
ABSTRACT:
A memory having a SRAM, a DRAM, and two independent and functionally identical IO ports. Each port may be used as a read-only, a write-only, or a read-write port. One port may perform a read access to the SRAM, whereas the other port may carry out a write access to the SRAM in the same clock cycle. Each and every location of the SRAM may be accessed from any of the ports. Each port comprises a two-stage pipelined data path for providing a read or write access to the SRAM. Stage 1 decodes control and write enable signals, latches address signals and performs the output of read data. Stage 2 supports accesses to SRAM cells for writing and reading data. In a unified-port mode of operation, two 16-bit ports may be combined to produce a single port supporting a 32-bit write or read access to the SRAM. In a data burst mode of operation, each port may be programmed to select individual length of data bursts and individual burst type.
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Camacho Stephen
Cassada Rhonda
Randolph William L.
Mitsubishi Electronics America Inc.
Robertson David L.
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