Multi-port memory systems and methods for bit line coupling

Details Multi-port memory systems and methods for bit line coupling Multi-port memory systems and methods for bit line coupling

2007-05-22

2007-05-22

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S189040, C365S194000, C365S230050

Reexamination Certificate

active

11054011

ABSTRACT:
Systems and methods provide bit line coupling detection techniques for multi-port memory applications. For example, in accordance with an embodiment of the present invention, a memory includes at least one column of memory having a plurality of memory cells and at least two ports and a dummy column having a dummy memory cell and a first port and a second port. At least one bit line is provided for each port of the columns of memory and the dummy column, with the dummy column adapted to provide a read timing indication by performing a write operation through the first port at substantially the same time as a read operation through the second port.

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patent: 6804153 (2004-10-01), Yoshizawa et al.

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