Multi-port memory device

Details Multi-port memory device Multi-port memory device

2006-02-28

2006-02-28

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Addressing

Multiple port access

C365S051000, C365S063000, C365S230030

Reexamination Certificate

active

07006402

ABSTRACT:
A multi-port memory device includes a plurality of banks arranged at an upper and a lower portion of a core area as many as a fixed number in a row direction, a multiplicity of ports located at edges of the upper and the lower portions of the core area, wherein respective ports perform independent communication with respective different target devices, a first global data bus, located in a row direction between the ports and the banks arranged at the upper portion of the core area, for performing the parallel data transmission, a second global data bus, located in a row direction between the ports and the banks arranged at the lower portion of the core area, for performing the parallel data transmission, many local data buses, arranged in a column direction of each bank, for executing data transmission within the banks, and a majority of local data bus connection units, located between two banks adjacent to each other in a column direction, for selectively connecting the local data buses corresponding to the two adjacent banks.

REFERENCES:
patent: 5812490 (1998-09-01), Tsukude
patent: 5867439 (1999-02-01), Asakura et al.
patent: 6809946 (2004-10-01), Fujisawa et al.
patent: 09-161476 (1997-06-01), None

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