Multi-port memory device

Details Multi-port memory device Multi-port memory device

2006-12-28

2010-11-16

Nguyen, Tuan T (Department: 2824)

Static information storage and retrieval

Addressing

Multiple port access

C365S230030, C365S189050

Reexamination Certificate

active

07835219

ABSTRACT:
A multi-port memory device including a plurality of ports, a plurality of banks and a plurality of bank controllers, wherein all of the bank controllers share all of the ports, the device includes a phase locked loop (PLL) unit for generating an internal clock signal; a delay unit, provided in each bank controller, for generating first and second delayed clock signals by delaying the internal clock signal; a serializer, provided in each bank controller, for receiving a plurality of parallel data from all of the ports and fitting the parallel data for a corresponding data frame in response to the first delayed clock signal; and a command decoder, provided in each bank controller, for decoding output data of the serializer to generate command signals in response to the second delayed clock signal.

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