Multi-port memory device

Details Multi-port memory device Multi-port memory device

2006-05-16

2006-05-16

Yoha, Connie C. (Department: 2827)

Static information storage and retrieval

Addressing

Multiple port access

C365S226000, C365S189090, C327S540000

Reexamination Certificate

active

07046576

ABSTRACT:
A multi-port memory device capable of preventing the first high data failure at an initial data transmission on a global data bus line according to the present invention includes: a global data bus line including a plurality of bus lines; a plurality of data transmitting and receiving unit including transmitters/receivers, which use a current sensing, for exchanging data into the global data bus line, wherein the receiver in the data transmitting and receiving unit includes resistors for dividing a voltage level; and a variable reference voltage generator for generating reference voltage levels as a receiver reference voltage, by controlling the resistance of the resistors in the receiver, wherein the variable reference voltage generator generates a first reference voltage level in an active mode and generates a second reference voltage level in a standby mode and wherein the first reference voltage level is higher than the second reference voltage level.

REFERENCES:
patent: 5373477 (1994-12-01), Sugibayashi
patent: 5856951 (1999-01-01), Arimoto et al.
patent: 6809576 (2004-10-01), Yamasaki

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