Multi-port memory controller having independent ECC encoders

Details Multi-port memory controller having independent ECC encoders Multi-port memory controller having independent ECC encoders

2007-04-17

2007-04-17

Sough, Hyung (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

C711S155000, C711S168000, C714S049000, C714S054000

Reexamination Certificate

active

10255912

ABSTRACT:
A memory controller system is provided, which includes a plurality of system buses, a multi-port memory controller and a plurality of error correcting code (ECC) encoders. The memory controller has a plurality of system bus ports and a memory port. Each ECC encoder is coupled between a respective system bus and a respective system bus port of the memory controller.

REFERENCES:
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patent: 5146461 (1992-09-01), Duschatko et al.
patent: 5459842 (1995-10-01), Begun et al.
patent: 6718444 (2004-04-01), Hughes
patent: 6792567 (2004-09-01), Laurent
patent: 2002/0053004 (2002-05-01), Pong
IEEE Spectrum, Adding Error-Correcting Circuitry to ASIC Memory, Apr. 2000, vol. 37, No. 4.

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