Multi-port memory circuit

Details Multi-port memory circuit Multi-port memory circuit

2005-04-26

2005-04-26

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Addressing

Multiple port access

C365S149000, C365S222000

Reexamination Certificate

active

06885608

ABSTRACT:
A memory cell includes first and second NMOS transistors and a capacitor that forms a storage node. During write operation, the first transistor is turned ON by a write address select circuit and a data bit is written on the storage node. During read operation, read bit lines are precharged, the second transistor is turned ON by a read address select circuit and the data bit held on the storage node is read. Data is read out without destruction when the storage node is at high logical level. However, if it has a low logical level, then a sense amplifier circuit outputs a low level and a refresh circuit writes a low level on the storage node.

REFERENCES:
patent: 6396764 (2002-05-01), Holland
patent: 6501701 (2002-12-01), Sadakata
patent: 6711048 (2004-03-01), Chien
patent: 6724645 (2004-04-01), Lanham et al.
patent: 6757200 (2004-06-01), Keeth et al.
patent: SHO 59-129989 (1984-07-01), None

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