Multi-port memory cell with refresh port

Details Multi-port memory cell with refresh port Multi-port memory cell with refresh port

2001-05-14

2003-04-08

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S222000

Reexamination Certificate

active

06545905

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to memory cells. More particularly, the invention relates to multi-port memory cells having improved performance.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs) such as digital signal processors (DSPs) include on-chip memory to store information. The on-chip memory typically comprises, for example, an array of static random access memory (SRAM) cells connected by word lines in one direction and bit lines in another direction. The information stored in the SRAM cells are maintained until power is removed from the IC. Sense amplifiers are coupled to the bit lines to facilitate memory accesses, such as reads or writes. A sense amplifier is coupled to a pair of bit lines and senses a differential voltage indicative of the information stored in the selected memory cell on the bit line pair.
FIG. 1
shows a conventional SRAM cell
101
. The SRAM cell comprises first and second transistors
110
and
120
coupled to a latch
130
, which stores a bit of information. One transistor is coupled to a bit line
140
and the other is coupled to a bit line complement
141
while the gates are coupled to a word line
135
. The latch includes first and second inverters
133
and
134
, each implemented with two transistors. As such, the SRAM cell is realized using six transistors.
Smaller SRAM cells using less than six transistors have been proposed to reduce chip size. However, the charge stored in such cells dissipates overtime. In order to restore the information stored in the cell, a refresh operation is required. Typically, refreshing of memory cells interrupt the normal operation, adversely impacting performance.
As evidenced from the above discussion, it is desirable to provide an improved memory cell in which refresh operations do not adversely impact performance.
SUMMARY OF THE INVENTION
The present invention relates generally to memory cells. More particularly, the invention relates to multi-port memory cells. In one embodiment, the memory cell comprises a plurality of first access transistors coupled to a first terminal of a storage transistor and a second access transistor coupled to a second terminal of the storage transistor. Bit lines are coupled to the access transistors and word lines are coupled to the gates of access transistors. In one embodiment, one of the access transistors serve as a dedicated refresh port of the memory cell.


REFERENCES:
patent: 4768172 (1988-08-01), Sasaki
patent: 5040146 (1991-08-01), Mattausch et al.
patent: 6118689 (2000-09-01), Kuo et al.

Affiliated with

Also associated with

Rating

Multi-port memory cell with refresh port does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-port memory cell with refresh port, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-port memory cell with refresh port will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3062401