Multi-port DRAM cell and memory system using same

Details Multi-port DRAM cell and memory system using same Multi-port DRAM cell and memory system using same

1996-12-17

1999-07-13

Mai, Son

Static information storage and retrieval

Read/write circuit

Simultaneous operations

365149, 36523005, G11C 700, G11C 800

Patent

active

059235934

ABSTRACT:
A multi-port DRAM cell structure that enables read, write and refresh accesses at each port of the DRAM cell. The DRAM cell includes a storage capacitor for storing a data value, and a plurality of ports for accessing the storage capacitor. Each port enables both read and write accesses to the storage capacitor. Each port can include a port access transistor, a port bitline and a port wordline. The port access transistor includes a gate electrode, a source and a drain. The source of the port access transistor is coupled to the storage capacitor, the drain of the port access transistor is coupled to the port bitline, and the gate electrode of the port access transistor is coupled to the port wordline. This cell architecture enables overlapping read and write accesses to be simultaneously performed at the various ports of the multi-port DRAM cell.

REFERENCES:
patent: 5007022 (1991-04-01), Leigh
patent: 5355335 (1994-10-01), Katsuno
patent: 5646903 (1997-07-01), Johnson
patent: 5768178 (1998-06-01), McLaury

Affiliated with

Also associated with

Rating

Multi-port DRAM cell and memory system using same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-port DRAM cell and memory system using same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-port DRAM cell and memory system using same will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2282931