Multi-port, bipolar-CMOS memory cell

Details Multi-port, bipolar-CMOS memory cell Multi-port, bipolar-CMOS memory cell

1990-03-27

1991-03-26

Bowler, Alyssa H.

Static information storage and retrieval

Systems using particular element

Semiconductive

365190, 36523005, 365191, 365154, G11C 700, G11C 1134, G11C 1140, G11C 11407

Patent

active

050035096

ABSTRACT:
A multi-port, BI-CMOS memory cell is disclosed having a CMOS flip-flop, one or more write ports gated by n-channel FETs, and one or more ECL read ports. Bipolar transistors in the read port are resistively interconnected to equalize emitter voltages during write and standby operations and to resistively isolate the emitters during a read operation.

REFERENCES:
patent: 4768172 (1988-08-01), Sasaki
patent: 4860263 (1989-08-01), Maltausch
patent: 4910711 (1990-03-01), Guo
patent: 4933899 (1990-06-01), Gibbs

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