Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2007-06-26
2007-06-26
Booth, Richard A. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C257SE21411
Reexamination Certificate
active
10862761
ABSTRACT:
A vertical thin-film transistor (V-TFT) inverter circuit and a method for forming a multi-planar layout TFT inverter circuit have been provided. The method comprising: forming a P-channel TFT with a gate, a first source/drain (S/D) region in a first horizontal plane, and a second S/D region in a second horizontal plane, different than the first horizontal plane; and, forming an N-channel TFT, adjacent the P-channel TFT, with a gate, a third S/D region in a third horizontal plane, and a fourth S/D region in the second horizontal plane, different than the third horizontal plane. Forming a P-channel TFT includes forming a P-channel top-drain vertical TFT (TDV-TFT), and forming an N-channel TFT includes forming an N-channel TDV-TFT.
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Schuele Paul J.
Voutsas Apostolos T.
Booth Richard A.
Law Office of Gerald Maliszewski
Maliszewski Gerald
Sharp Laboratories of America Inc.
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