Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent
1997-01-06
1998-07-28
Voeltz, Emanuel Todd
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
711127, 711140, 711157, 36496426, 395677, 395556, 395559, G06F 1567, G06F 1318
Patent
active
057874883
ABSTRACT:
A multi-phase, multi-access pipeline memory system includes a number, n, of processors; a pipeline memory including a latch; and a bus for interconnecting the processors and pipeline memory; a clock circuit responsive to a system clock signal divides the system clock signal into n phases for providing multiple clock signals corresponding to the n phases of the system clock signal for application to each processor to allow data and address to be transferred only during its assigned phase thereby enabling the memory and each processor to operate at the system clock rate while allowing n accesses to the memory during each system clock signal period, one access for each processor.
REFERENCES:
patent: 4392200 (1983-07-01), Arulpragasan et al.
patent: 5010476 (1991-04-01), Davis
patent: 5297267 (1994-03-01), Inoue
"CPC (Cyclic Pipeline Computer)--An Architecture Limited for Josephson and Pipelined-Memory Machines", by Shimuzu, K. et al, IEEE Transactions on Computers, Jun. 1989.
Analog Devices Inc.
Richey Michael T.
Todd Voeltz Emanuel
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