Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reissue Patent
2004-08-27
2009-10-20
Kim, Kevin Y (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S374000
Reissue Patent
active
RE040939
ABSTRACT:
The present invention provides a multi-phase-locked loop without dead zone, which can reduce clock jitter and provide larger tolerance for data random jitter. It generates and output multiple sets of control signals (upk/dnk) via a multi-phase voltage controlled oscillator which generates a plurality of multi-phase clock signals for detecting the transition edge of data signal. Therefore, the phase error θeand the voltage Vd of the multi-phase-locked loop can be adjusted to be nearly linear according to the control signals. A multi-phase-locked loop without dead zone thus can be provided.
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Kim Kevin Y
Realtek Semiconductor Corporation
Thomas Kayden Horstemeyer & Risley
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