Multi-phase-locked loop for data recovery

Details Multi-phase-locked loop for data recovery Multi-phase-locked loop for data recovery

1999-06-14

2002-08-27

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S374000

Reexamination Certificate

active

06442225

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a phase-locked loop for data recovery, and more particularly, to a multi-phase-locked loop that utilizes a multi-phase clock signal generated by a multi-phase voltage controlled oscillator (VCO) to detect received data.
BACKGROUND OF THE INVENTION
Due to the development of the network transmission technology as well as the demands in the installed base of computer networks, the network data transmission rate in hardware environment has been increased. Therefore, it becomes more and more important to recover data (clock signals) correctly.
At present, while data (clock) recovery is to be performed, a phase-locked loop is often utilized. During the data recovery process, usually the received data could be correctly recovered (read) by using a phase detector to synchronize the received data and recover the clock. In other words, the phase detector plays a very important role whether the data could be correctly recovered by a phase-locked loop.
FIG. 1
illustrates a prior art phase-locked loop for data recovery comprising a phase detector
11
, a charge pump
12
, a loop filter
13
, and a voltage controlled oscillator
14
. The phase detector
11
is used to receive a data (clock) signal from outside as well as a feedback clock signal CK
vco
from the voltage controlled oscillator
14
. The phase detector
11
compares the two signals, in accordance with their phase difference &thgr;
e
(&thgr;
e
=&thgr;
data
−&thgr;
clock
), a control signal up or dn will be output to control the charge pump
12
. As shown in FIG.
2
(
a
), when the transition edge of the data (clock) signal data leads the falling edge of the feedback clock signal CK
vco
, the phase detector outputs an up signal. On the other hand, as shown in FIG.
2
(
b
), when the transition edge of the data (clock) signal data lags behind the falling edge of the feedback clock signal CK
vco
, the phase detector
11
outputs a dn signal. The charge pump
12
is controlled by the up and dn control signals output from the phase detector
11
to perform charge/discharge operations, and generates a voltage signal Vd. The loop filter
13
receives the voltage signal Vd and generates an appropriate voltage Vc for controlling the voltage controlled oscillator
14
. The voltage controlled oscillator
14
receives the voltage Vc and generates a clock signal CK
vco
to be input to the phase detector
11
.
As shown in
FIG. 3
, the phase detector
11
of the phase locked loop
1
is constituted by four flip-flops
111
,
112
,
113
,
114
, and two OR gates
115
,
116
. The flip-flops
111
and
112
receive the complement of data from outside (denoted by {overscore (data)}) and the data itself (denoted by data), respectively. The clock signal CK
vco
from the voltage controlled oscillator
14
is applied to the inversion reset terminals (rb) of the flip-flops
111
and
112
such that two control signals up
1
and up
2
are generated, respectively. The flip-flops
113
and
114
receive the complement of data from outside (denoted by {overscore (data)}) and the data itself (denoted by data), respectively. The complement of the clock signal CK
vco
(denoted by {overscore (CK
vco
+L )}) from the voltage controlled oscillator
14
is applied to the inversion reset terminals (rb) of the flip-flops
113
and
114
such that two control signals dn
1
and dn
2
are generated, respectively. According to the two signals up
1
and up
2
, the OR gate
115
generates a control signal up for controlling the charge pump
12
(refer to FIG.
2
(
a
)). Similarly, the OR gate
116
generates a control signal dn for controlling the charge pump
12
according to the two signals dn
1
and dn
2
(refer to FIG.
2
(
b
))
Referring to
FIG. 1
, the voltage Vd is substantially controlled by the signals (up, dn). In other words, the variation of the control voltage Vd is related to the phase error &thgr;
e
.
FIG. 4
illustrates the relation between the variation of Vd and the phase error &thgr;
e
. As shown in
FIG. 4
, when the data signal data has a phase lagging behind the clock signal CK
vco
, the smaller the phase error &thgr;
e
is, the more the voltage Vd varies. Therefore, phase error &thgr;
e
is theoretically supposed to approximate to zero and closely moves around the origin when the phase-locked loop is going to enter a phase-locked state. However, due to the above phenomenon, when the data signal data of the phase-locked loop has a phase lagging behind the clock signal CK
vco
, an obvious variation of Vd will be generated, which leads to clock jitter. And, the tolerance for data random jitter becomes worse. In other words, it is difficult to reduce the clock jitter for conventional phase-locked loops, large data random jitter is thus unaccepted.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a multi-phase-locked loop without dead zone, which can reduce clock jitter and provide higher tolerance for data random jitter.
Another object of the present invention is to provide a multi-phase-locked loop without static phase error.
The present invention is characterized by a multi-phase-locked loop which can generate a plurality of multi-phase clock signals by a multi-phase voltage controlled oscillater to detect the transition edge of the data signal data. Accordingly, multiple sets of control signals (up
k
/dn
k
) are generated. Therefore, phase error &thgr;
e
and voltage Vd of the multi-phase-locked loop can be adjusted to be nearly linear according to the output control signals. This prevents the multiphase-locked loop from having dead zone. Furthermore, the clock jitter can be reduced and provide greater tolerance for data random jitter.
To achieve the aforementioned object, a multiphase-locked loop for data recovery in accordance with the invention includes a phase detector, a charge pump, a loop filter and a voltage controlled oscillator (VCO).
The phase detector is constituted by N phase detection units (U
1
, U
2
, . . . , U
N
, N is even, N≧4). The phase detection units are connected in cascade configuration, and each of the phase detection unit contains a data signal input terminal for receiving the data signal from outside; a clock signal input terminal for receiving the multi-phase clock signals (CK
1
, CK
2
, . . . , CK
N
) from outside; a delay signal input terminal for receiving the delay signal output from another phase detection unit; a delay signal output terminal for outputting the delay signal; and a charge/discharge control signal output terminal for outputting charge/discharge control signals. Each phase detection unit generates a delay signal (D
1
, D
2
, . . . , D
N
) according to the input data signal and the complement of the multi-phase clock signal.
The delay signal (D
j+1
) generated by the (j+1)
th
phase detection unit is applied to the j
th
phase detection unit via the j
th
delay signal input terminal. The delay signal (D
1
) generated by the first phase detection unit (U
1
) is applied to the N
th
phase detection unit (U
N
) via the N
th
delay signal input terminal. In addition, the j
th
phase detection unit (U
j
′1≦j≦N′j is an integer) generates control signals (dn
1
, dn
2
, . . . , dn
N/2
, up
N/2
, . . . , up
2
) for the charge/discharge operations according to the delay signal (D
j
) from the j
th
phase detection unit, the delay signal (D
j+1
) from the (j+1)
th
phase detection unit, and the multi-phase clock signal (CK
j
) which is applied to the j
th
phase detection unit. However, the N
th
phase detection unit (U
N
) generates a charge control signal (up
1
) according to the delay signal (D
N
) from the N
th
phase detection unit, the delay signal (D
1
) from the first phase detection unit, and the multi-phase clock signal (CK
N
) which is applied to the N
th
phase detection unit.
The charge pump is constituted by N/2 charge and discharge units (CP
1
, CP
2
, . . . , CP
N/2
), wherein the k
th
(1≦k≦N/2) charge and discharge unit (CP
k
) re

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