Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1997-11-10
2001-07-24
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06266799
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuit devices used for processing data through communication networks, and more particularly, to methods and apparatus for implementing data/clock recovery systems in networking circuitry.
2. Description of the Related Art
In view of the recent push to develop faster networking technology, networking companies have been required to design circuitry that is sufficiently fast to process data at increased speeds. As an example, a number of computer network companies have been working on the development of gigabit Ethernet networking products that are in compliance with the IEEE 802.3z standard (1000 Mbps-Gigabit Ethernet). Although there has been significant progress in increasing data transfer rates to gigabit speeds and greater, much of the core circuitry that is currently implemented in Ethernet transceivers is lagging the advancement in other core gigabit Ethernet circuitry.
A core part of a gigabit Ethernet circuit is the physical level circuitry that is used to interface over a physical media to other network devices. As is well known, transceivers that are integrated into the physical level circuitry must have superior speed, processing integrity and integration flexibility with other existing network circuitry. Typically, the transceivers use analog phase locked loop (PLL) circuitry to do the data/clock recovery. The data clock recovery circuit uses a VOC to generate the multiple phase clocks that run at a lower rate than baud rate to over-sample and latch incoming high speed serial data streams. The multiple sampled data is then fed to multiple phase detectors in parallel, and the outputs of the phase detectors drive multiple charge pump circuits. Each of the charge pumps then drive a single analog loop filter. The output of the loop filter then controls a VCO output frequency.
Unfortunately, the conventional analog data/clock recovery circuits are harder to design and difficult to integrate with digital media access controller (MAC) circuitry. In addition, crosstalk between a transmitter's analog PLL and a receiver's analog PLL is known to cause excessive jitter problems when these circuits are integrated with traditional CMOS network circuitry. As a result, the conventional analog PLL solutions introduce performance reducing side effects that make them incompatible with many of today's high speed networking circuit components.
In view of the foregoing, there is a need for a digital data/clock recovery system that is capable of processing data at high speeds.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing methods and apparatuses for a multi-phase data/clock recovery system for use in high speed networking circuit applications. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, a method, or a computer readable medium. Several inventive embodiments of the present invention are described below.
In one embodiment, a multi-phase data/clock recovery circuit is disclosed. The circuitry includes a phase sampler circuit that is configured to receive a data input waveform and produce output data. A transition detect circuit that is arranged to receive the output data produced by the phase sampler circuit. The transition detect circuit is configured to determine whether a clock is leading or lagging the data input waveform. The circuit further includes a counter for shifting the clock if the clock is determined by the transition detect circuit to either be leading or lagging the data input waveform, whereby the shifting is configured to synchronize the clock and the data input waveform.
In another embodiment, a data/clock recovery system is disclosed. The data/clock recovery system includes a four phase sampler circuit that is configured to receive a data input waveform and produce output data. A transition detect circuit that is arranged to receive the output data produced by the four phase sampler circuit. The transition detect circuit is configured to determine whether a clock is leading or lagging the data input waveform. A counter for shifting the clock if the clock is determined by the transition detect circuit to either be leading or lagging the data input waveform, such that the shifting is configured to synchronize the clock and the data input waveform. A decoder that receives a control signal from the counter, such that the decoder generates a selection signal. The data/clock recovery system further including a multiplexer for selecting four predetermined clock phases in response to the selection signal generated by the decoder. Preferably, the four predetermined clock phases are continually shifted by the counter if the clock and the data input waveform are not synchronized.
In yet another embodiment, a method for synchronizing a data stream with a clock of a transceiver is disclosed. The method includes receiving a data stream. Selecting a set of clock phases that are configured to sample the received data stream, such that each phase of the set of clock phases have an inter-phase separation. Examining the received data stream after being sampled with the set of clock phases. The method further includes shifting the clock of the transceiver when the examining indicates that the clock is lagging or leading the data stream. Preferably, the examining is performed on two bits of the data stream at one time, thereby reducing the processing load of a high speed data stream.
In still another embodiment, a method for implementing a data/clock recovery system in a network device receiver is disclosed. The network device receiver is configured to receive a serial data stream from a remote network device. The method includes producing a plurality of clock phases for every two bits of the serial data stream. Selecting four clock phases from the plurality of clock phases, such that the four clock phases have a predetermined separation. Analyzing the serial data stream that corresponds to the selected four clock phases to determine whether a new four clock phases should be selected from the plurality of clock phases. Selecting the new four clock phases when the analyzing indicates that the selected four clock phases and the serial data stream are not synchronized. Wherein the new four clock phases are selected to prevent the selected four clock phases from leading or lagging the serial data stream.
In another embodiment, a data/clock recovery circuit is an important feature of a receiver for gigabit transceiver applications. A data/clock recovery circuit (as shown in
FIG. 3
below) is based on the multiple phase clocks to over-sample the incoming serial data stream and a multi-phase digital phase locked loop (DPLL) to shift and rotate unlimitedly four sampling phases, which are selected from the multi-phase clock generator. Every two serial NRZ data bits are sampled with four sampling phases. The first sampling phase and the fourth sampling phase are separated exactly at a bit-time, and they should be located at the centers of the data eyes, once they have locked with the incoming data. The second sampling phase and the third sampling phase are separated at a quarter of the bit time as shown in
FIG. 6A
below.
The first and second sampling phases should be separated at three eighth of the bit-time. The third and fourth sampling phases should be also separated at three eighth of the bit-time. After the input four phase sampler, a NRZ data transition detection circuit and a lead-lag decision circuit are used to decide whether the first and the fourth sampling phases are at the centers of their respective data eyes. The lead-lag decision circuit will generate the UP control signal or the DOWN control signal, or NO CHANGE to control a 4 bit up-and-down counter. The output of the counter will be decoded into one selective line which in turn controls a multiplexer to select the four sampling phases from the multi-phase c
Lee Lance K.
Shyu Jyn-Bang
Wang David Y.
Beyer Weaver&Thomas, LLP
Do Thuan
Smith Matthew
Xaqti Corporation
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