Multi-phase clock generator and multiplier

Details Multi-phase clock generator and multiplier Multi-phase clock generator and multiplier

1994-10-03

1995-07-25

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

331 57, 331108R, H03D 324

Patent

active

054369398

ABSTRACT:
A multiphase clock generator which exhibits frequency stability in the presence of power supply noise. The clock generator of the present invention includes a phase detector for generating a phase error signal in response to the phase difference between an input signal and a recovered clock signal. A phase-locked feedback loop is operative to synthesize a recovered clock signal in response to the phase error signal. Included within the feedback loop is a differential ring oscillator disposed to provide first and second phase-shifted output signals at first and second output ports. The addition of a combination network to the multiphase clock generator of the present invention allows a multiplied clock signal to be derived from an input signal. Specifically, the phase-locked feedback loop 18 included within the clock multiplier of the present invention provides a plurality of sequentially phase-shifted waveforms at a first multiple of the frequency of the input signal. The phase-shifted waveforms are then combined into the output clock signal at a second multiple of the frequency of the input clock signal.

REFERENCES:
patent: 5059924 (1991-10-01), JenningsCheck
patent: 5073905 (1991-12-01), Dapper et al.
patent: 5119045 (1992-06-01), Sato
patent: 5175512 (1992-12-01), Self
patent: 5180994 (1993-01-01), Martin et al.
patent: 5191301 (1993-03-01), Mullgrav, Jr.

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