Multi-phase clock distribution method and system for complex int

Details Multi-phase clock distribution method and system for complex int Multi-phase clock distribution method and system for complex int

1997-03-28

1999-10-12

Teska, Kevin J.

39550007, G06F 1750

Patent

active

059665220

ABSTRACT:
A system and method are provided for distributing clock signals within integrated circuitry. The system includes a number of cells for the integrated circuitry such that the cells include substantially horizontal regions within which are disposed substantially horizontal lines representative of a first clock. The cells also include substantially vertical regions within which are disposed vertical lines representative of a second clock. The cells are disposed in substantially horizontal layers. The vertical regions, including the vertical lines representative of a second clock are substantially vertically aligned. The cells include circuitry disposed within each cell such that a first portion of such circuitry includes signal wiring, and a second portion of such circuitry includes clock wiring, and such that the disposition of said circuitry minimizes a cumulative length of signal wiring and clock wiring.

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