Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2004-03-31
2010-10-12
Thai, Tuan V. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S100000, C711S154000
Reexamination Certificate
active
07814278
ABSTRACT:
A system may include several nodes coupled by an inter-node network. Each node includes several active devices, a memory subsystem, and an address network and a data network respectively configured to convey address packets and data packets between the active devices and the memory subsystem. The memory subsystem included in one of the nodes is configured to maintain a response indication indicating whether the memory subsystem should send a data packet corresponding to a coherency unit in response to receiving an address packet requesting an access right to the coherency unit from an active device in the same node. The node is also configured to store a node identifier for the coherency unit. The node identifier identifies which of the nodes that has the coherency unit is in a modified global access state.
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Meyertons Hood Kivlin Kowert & Goetzel P.C.
Oracle America Inc.
Thai Tuan V.
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