Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-08-30
2011-08-30
Thai, Tuan V. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S100000, C711S118000, C711S154000
Reexamination Certificate
active
08010749
ABSTRACT:
A node includes several devices including a memory, an active device, and an interface configured to send and receive coherency messages on an inter-node network coupling the node to another node, as well as an address network and a data network. In response to receiving a coherency message requesting an access right to a coherency unit, the interface is configured to send a first type of address packet on the address network if the global access state of the coherency unit within the node is the modified state and a second type of address packet otherwise. The memory is configured to respond to receipt of the second type of address packet by sending a data packet on the data network, regardless of whether the memory currently has an ownership responsibility for the coherency unit.
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Cypher Robert E.
Hagersten Erik E.
Landin Anders
Meyertons, Hood, Kilvin, Kowert & Goetzel, P.C.
Oracle America Inc.
Thai Tuan V.
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