Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2004-04-09
2009-10-20
Kim, Matt (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S122000, C711S142000, C711S143000, C711S144000, C711S145000, C711S146000, C711S147000, C711S148000, C709S213000, C709S214000, C709S215000, C709S216000
Reexamination Certificate
active
07606978
ABSTRACT:
A node in a multi-node system includes a memory, an active device that includes a cache, an interface that sends and receives coherency messages on an inter-node network coupling the node to another node, and an address network that communicates address packets between the devices in the node. In response to receiving a coherency message from the other node requesting an access right to a coherency unit, the interface sends an address packet on the address network. The address packet is a first type of address packet if the coherency unit is in the modified global access state in the node and a second type of address packet otherwise. If the active device is the owner of the coherency unit, the active device responds to the first type of address packet and ignores the second type of address packet.
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Cypher Robert E.
Hagersten Erik E.
Landin Anders
Kim Matt
Kivlin B. Noëel
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Patel Kaushikkumar
Sun Microsystems Inc.
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