Multi-node chipset lock flow with peer-to-peer non-posted...

Details Multi-node chipset lock flow with peer-to-peer non-posted... Multi-node chipset lock flow with peer-to-peer non-posted...

2011-08-09

2011-08-09

Tsai, Henry W (Department: 2184)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output command process

C712S022000

Reexamination Certificate

active

07996572

ABSTRACT:
Systems and methods of managing transactions provide for receiving a first flush command at a first I/O hub, wherein the first flush command is dedicated to non-posted transactions. One embodiment further provides for halting an inbound ordering queue of the first I/O hub with regard to non-posted transactions in response to the first flush command and flushing a non-posted transaction from an outgoing buffer of the first I/O hub to a second I/O hub while the inbound ordering queue is halted with regard to non-posted transactions.

REFERENCES:
patent: 6009488 (1999-12-01), Kavipurapu
patent: 6457084 (2002-09-01), Gulick et al.
patent: 6950438 (2005-09-01), Owen et al.
patent: 2002/0103948 (2002-08-01), Owen et al.

Affiliated with

Also associated with

Rating

Multi-node chipset lock flow with peer-to-peer non-posted... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-node chipset lock flow with peer-to-peer non-posted..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-node chipset lock flow with peer-to-peer non-posted... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2746327