Multi-mode testing systems

Details Multi-mode testing systems Multi-mode testing systems

1988-12-29

1990-12-25

Smith, Jerry

Excavating

371 221, G06F 1100

Patent

active

049808893

ABSTRACT:
A multi-mode testing system is provided which includes first, second and third selector circuits, each of which has a control circuit for selecting one of first and second paths connected to an output, and a single shift register latch having first and second input ports and an output. The first path of the first selector circuit and of the second selector circuit is connected to a data output terminal of a logic circuit under test and the output of the third selector circuit is connected to a data input terminal of the logic circuit under test. A driver circuit has an input connected to the output of the first selector circuit and an output connected to an input/output terminal, with the input/output terminal also being coupled to the first path of the third selector circuit and to the second path of the second selector circuit. The first input port of the latch is connected to the output of the second selector circuit, the second input port is coupled to a scan data input terminal and the output of the latch is connected to the second path of the first selector circuit and of the third selector circuit.

REFERENCES:
patent: 3771131 (1973-11-01), Ling
patent: 4167780 (1979-09-01), Hayashi
patent: 4216539 (1980-08-01), Raymond
patent: 4488259 (1984-12-01), Mercy
patent: 4799004 (1989-01-01), Mori
IEEE Digest of Papers, Proceedings of the International Test Conference, 1982, pp. 414-424, "LSI Self-Test Using Level Sensitive Scan Design and Signature Analysis", by D. Komonytsky.

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