Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1993-02-01
1995-07-25
Chin, Stephen
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
375368, 375259, H03D 324
Patent
active
054369371
ABSTRACT:
A multi-mode PLL circuit (100) includes an early/late bit transition accumulator (108) for accumulating the number of incoming bit transitions which are early or late. This allows for PLL (100) to provide adjustments based on a predetermined number of accumulated early/late accumulations or based on an average of early/late transitions over a predetermined period of time. PLL (100) further includes a frequency offset circuit (200) which includes a frequency error accumulator which is used to maintain a frequency offset history and to control the loop frequency. This allows for very narrow band operation of the first order digital PLL while maintaining stable operation.
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CT2 Common Air Interface Version 1.1, 6/30/91, 188 pages, "Common air interface specification to be used for the interworking between cordless telephone apparatus in the frequency band 864.1 MHz to 868.1 MHz, including public access services" European Telecommunications Standards Institute, Valbonne Cedez France.
Brown David L.
Marko Paul D.
Chin Stephen
Motorola Inc.
Nichols Daniel K.
Phan Hai H.
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