Multi-master computer system with overlapped read and write...

Details Multi-master computer system with overlapped read and write... Multi-master computer system with overlapped read and write...

2001-05-15

2004-08-03

Lefkowitz, Sumati (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S113000, C710S305000

Reexamination Certificate

active

06772254

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of Invention
This invention relates to information processing systems, methods of operation and program products. More particularly, the invention relates to Processing Local Bus (PLB) architecture for multi-master and slave data transfers with overlapped read/write operations and scalable address pipelining: systems, methods and program products.
2. Description of Prior Art
Microprocessor based system central processing units and other bus masters require access to main memory locations. Main memory is typically distanced from the masters by at least one level of bridging between the masters and the memory bus. This bridging function is accomplished via a memory controller. The memory controller can be a sophisticated mechanism capable of accepting and ordering several different memory operations at any given moment in time. One of the problems associated with memory control is the initial memory latency inherent with dynamic random access memory, or DRAM. From the time that a master or CPU initiates a read request to main memory until the data is returned can be well over a dozen bus clock cycles. This latency negatively affects the overall system performance. To counteract the latency effect on reads to main memory the concept of “address pipelining” was introduced whereby the master would present a subsequent pending read request to the memory controller prior to completion of a preceding read operation. In this way the memory controller could better order and schedule use of the memory bus to decrease overall latency on subsequent pending reads. Also, other devices attached to the bus could claim operations destined for them in the future and allocate resources so that their initial latency is reduced. Further arbitration cycles, which use to operate sequentially with read and write transfers may now be performed in parallel with previous transfer requests in progress. What is needed in the art is a scalable address pipelining mechanism in a PLB architecture which can be used to programmably increase the depth of address pipelining independently on two overlapped read and write data buses while one operation is being performed and another operation is being performed at the same time.
Prior art related to address pipelining includes:
1. U.S. Pat. No. 6,081,860 entitled “Address Pipelining for Data Transfer,” issued Jun. 27, 2000 filed Nov. 20, 1997 discloses a process and system for transferring data including at least one slave device connected to at least one master device through an arbiter device. The master and slave devices are connected by a single address bus, a write data bus and a read data bus. The arbiter device receives requests for data transfers from the master devices and selectively transmits the requests to the slave devices. The master devices and the slave devices are further connected by a plurality of transfer qualifier signals, which may specify predetermined characteristics of the requested data transfers. Control signals are also communicated between the arbiter device and the slave devices to allow appropriate slave devices to latch addresses of requested second transfers during the pendency of current or primary data transfers so as to obviate an address transfer latency typically required for the second transfer. The design is configured to advantageously function in mixed systems, which may include address-pipelining and non-address-pipelining slave devices.
2. U.S. Pat. No. 4,626,843 entitled “Multi-Master Communication Bus System with Parallel Bus Request Arbitration” issued Dec. 2, 1986 discloses apparatus and a related method for regulating access to a communication bus to which multiple communication nodes are connected. Control logic at each of the nodes determines which of them has priority to access the bus, by means of a parallel arbitration sequence in which all nodes contending for bus access participate. Specifically, each contending node generates a relative priority node number and asserts it onto an arbitration bus. All of the asserted node numbers are logically combined into a composite node number on the bus, and the winning node is determined in a bit-by-bit ripple comparison circuit at each node, the composite node number being compared with the locally generated relative priority node number. Priority is determined in advance of data transmission, and synchronization and arbitration take place without any central or master control unit.
3. U.S. Pat. No. 5,555,425 entitled “Multi-Master Bus Arbitration System in Which the Address and Data Lines of the Bus May Be Separately Granted to Individual Masters,” issued Sep. 10, 1996 discloses a multi-master digital computer system has a bus, a plurality of master devices connected to the bus, a plurality of slave devices connected to the bus, and a bus controller for arbitrating bus requests by the master devices and for granting the bus to a selected one of the plurality of the master devices. Each master device is capable of originating a bus cycle to transmit data to or receive data from a desired slave device. The bus controller grants the bus to a selected master device, which enters an address master state and addresses the desired slave device. The selected master device is transferred to a bus master state where a data transfer to or from the slave device is initiated. The selected master device then transfers to a data master state unless the selected master device wants, and is permitted through an arbiter, to retain control of the bus. The bus controller grants a bus request to a requesting master device through to the arbiter. The requesting master device is transferred into the address master state while the selected master device is still in the data master state, thus performing a pipelining operation.
4. U.S. Pat. No. 5,640,527 entitled “Apparatus & Method for Address Pipelining of Dynamic Random Access Memory Utilizing Transparent Page Address Batches to Reduce Wait States,” issued Jun. 17, 1997 discloses An apparatus and method for address pipelining of a computer system that reduce the average number of wait states required to access a dynamic random access memory (DRAM) subsystem. A memory controller addresses a plurality of random access memory integrated circuits in pages of addresses wherein contiguous address pages are in different ones of the plurality of dynamic random access memory integrated circuits. Transparent latches associated with each of the different ones of the plurality of dynamic random access memory integrated circuits allow pipelining of address setups for more than one memory page at substantially the same time. The apparatus and method improve the write access times of a computer system and, when used with a computer system having address pipelining, both read and write accesses are improved because address set up latency time is reduced.
5. U.S. Pat. No. 5,699,516 entitled “Method & Apparatus for Implementing In-Order Termination Bus Protocol Within a Data Processing System,” issued Dec. 16, 1997 discloses a bus protocol is provided for pipelined and/or split transaction buses (
18
,
48
) which have in-order data bus termination and which do not require data bus arbitration. The present invention solves the problem of matching the initial address request by a bus master (
12
,
13
,
42
) to the corresponding data response from a bus slave (
14
,
15
,
44
) when the bus (
18
,
48
) used for master-slave communication is a split-transaction bus and/or a pipelined bus. Each bus master (
12
,
13
,
42
) and each bus slave (
14
,
15
,
44
) has a counter (
30
-
33
,
75
-
76
) which is used to store a current pipe depth value (
21
,
51
) from a central pipe counter (
16
,
72
). A transaction start signal (
20
,
50
) and a transaction end signal (
22
,
52
) are used to selectively increment and decrement the counters (
30
-
33
,
75
-
76
).
6. U.S. Pat. No. 5,440,751 entitled “Burst Data Transfer to Single Cycle Transfer Conversion and Stroke Single Conversion,” issued Aug. 8, 1995 discloses an apparatu

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