Multi-master, chained two-wire serial bus

Details Multi-master, chained two-wire serial bus Multi-master, chained two-wire serial bus

2006-03-17

2009-12-15

Knoll, Clifford H (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S310000

Reexamination Certificate

active

07634611

ABSTRACT:
Aspects of the disclosure embody a multi-master two-wire serial bus that comprises two or more chained two-wire serial busses. The chained two-wire serial busses include a host two-wire serial bus with a first master device and one or more slave devices. One or more chained two-wire serial busses are coupled to the host bus wherein one or more slave devices on the host two-wire serial bus operate as second master devices, which comprise a digital state machine including a two-wire serial slave component coupled to the master device and a two-wire serial master component coupled to the slave devices on the chained two-wire serial bus. The digital state machine emulates a slave device on the host two-wire serial bus and a master device on the chained two-wire serial bus.

REFERENCES:
patent: 2004/0255195 (2004-12-01), Larson et al.
patent: 2005/0246475 (2005-11-01), Ervin
“The I2C-Bus Specification,” Version 2.1, Jan. 2000, Phillips Semiconductors, p. 1-46.
“Dual Bidirectional I2C-Bus and SMBus Repeater,” Texas Instruments, SCPS150-Dec. 2005.
“The I2C-bus and how to use it (including specifications),” 1995 Update, Apr. 1995, Phillips Semiconductors, p. 1-24.

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