Multi-logic device systems having partial crossbar and...

Details Multi-logic device systems having partial crossbar and... Multi-logic device systems having partial crossbar and...

1999-02-09

2003-08-05

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C326S038000, C326S047000, C326S101000

Reexamination Certificate

active

06604230

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to architectures for multi-programmable logic device systems such as systems used for design verification. More specifically, the present invention relates to architectures for hardware logic emulation systems of electronic systems. The present invention also relates to architectures for systems used to rapidly prototype large digital electronic designs and programmable hardware implementation of algorithms (e.g., computation).
BACKGROUND OF THE INVENTION
Field Programmable Gate Arrays and other programmable logic chips (collectively referred to herein as FPGAs) are integrated circuits that can be programmed to implement various logical functions and are either one-time programmable or reprogrammable. FPGAs are widely used for implementing digital circuits because they offer moderately high levels of integration and faster implementation than other types of logic devices such as gate arrays and application specific integrated circuits (“ASICs”). Multi-FPGA systems (referred to herein as “MFSs”) are collections of FPGAs joined together by a various interconnection schemes or topologies. MFSs are used when the logic capacity of a single FPGA is insufficient to implement a specific logic design. Reprogrammable FPGAs are used when quickly reprogrammable systems are desired.
The routing architecture of an MFS is the manner in which the FPGAs, fixed wires on the printed circuit boards (“PCBs”) and programmable interconnect chips are connected. The choice of the routing architecture used to interconnect the FPGAs has a significant effect on the speed and cost of the system.
MFSs are used in various different technologies, including logic emulation, rapid prototyping, and reconfigurable custom computing machines. Examples of MFSs used for logic emulation, rapid prototyping and reconfigurable computing machines can be seen in U.S. Pat. Nos. 5,036,473, 5,448,496, 5,452,231, 5,109,353 and 5,475,830. The disclosures of U.S. Pat. Nos. 5,036,473 , 5,448,496, 5,452,231, 5,109,353 and 5,475,830 are incorporated herein by reference in their entirety.
Hardware logic emulation is an important application for MFSs. Hardware logic emulation systems map a structural representation (commonly referred to as a netlist) of logic design such as an ASIC or a microprocessor into an MFS. In a hardware emulation system, the logic design is operated at speeds that approach real time, i.e., the speed at which the target system (the system where the actual fabricated integrated circuit will be installed) will operate. Thus, hardware logic emulation systems can emulate logic designs at speeds ranging from hundreds of Kilohertz to a few Megahertz. These speeds are several orders of magnitude faster than software design simulation speeds, which are generally restricted to at most few tens of Hertz.
Thus, hardware emulation allows functional verification of a design in its target operating environment, which includes other hardware and software modules. Many functional errors in the logic design that might not have been detected using traditional design verification methods such as software simulation can be discovered and fixed prior to fabrication of the actual integrated circuit. This is due to software simulation's long execution times. Thus very costly iterations in integrated circuit fabrication can be avoided. Reducing or eliminating the number of iterations results in reduced design costs and faster time-to-market, which are crucial in today's competitive technology market.
Many MFSs and associated CAD tools have been proposed and built for logic emulation, rapid prototyping and a wide variety of applications in custom computing. Prior art MFSs that have been previously developed range from small systems that fit on a single printed circuit board (PCB) to huge systems that use hundreds of FPGAs laid out on multiple PCBs, which in turn are mounted in many card cages and chassis. Examples of small, single PCB, prototyping systems are the MP3™ and MP4™ prototyping systems available from Aptix Corporation of San Jose, Calif. Examples of large emulation systems are the Mercury™ and System Realizer™ emulation systems available from Quicktum Design Systems, Inc. San Jose, Calif.
Overwhelming majorities of MFSs have been implemented on PCBs. However, a few MFSs based on Multi-Chip Modules (MCMs) have been proposed and built. In these Field-Programmable Multi-Chip Modules (FPMCMs), several FPGA dies are mounted on a surface within the MCM package. Interconnection resources are provided and all the logic and routing resources are packaged as a single unit. The advantages of MCM-based MFSs compared to PCB-based MFSs are reduced size, power consumption and superior speed performance. While the present application specifically refers to PCB-based implementations, the teachings of the present invention are equally applicable to MCM-based MFSs.
The routing architecture of an MFS is defined by the topology used to interconnect the FPGAs. Another distinguishing feature is whether programmable interconnect devices, also called field programmable interconnect devices (“FPIDs”), programmable interconnect chips (“PICs”) or crossbars by those skilled in the art, are used for connecting the FPGAs. FPIDs can be implemented using interconnect chips, logic devices having sufficient interconnect resources and FPGAs available from such vendors as Xilinx Corporation of San Jose, Calif. and Altera Corporation of San Jose, Calif.
Prior art routing architectures can be categorized roughly in the following three ways: FPGA-only architectures, architectures that use only FPIDs for interconnecting FPGAs, and architectures that use both FPGAs and FPIDs for interconnecting FPGAs.
FPGA-only Architectures
In FPGA-only architectures, only direct hardwired connections between FPGAs are used. Thus, there are no programmable connections through FPIDs because no FPIDs are present. This class of architecture can be further sub-divided into the following three categories: linear arrays, mesh architectures, and graph connected architectures (which as will be seen below, are subdivided into three categories). These different types of FPGA-only architectures will now be described.
An example of an MFS having a linear array architecture can be seen in FIG.
1
. In MFSs utilizing a linear array architecture, the FPGAs
10
a
-
10
f
are arranged in the form of a linear array, which is suitable for one-dimensional systolic processing applications. Thus, each FPGA
10
a
-
10
f
is directly connected to the FPGA
10
a
-
10
f
linearly adjacent thereto. Using the example of
FIG. 1
, FPGA
10
b
is directly connected to FPGA
10
a
and FPGA
10
c
. Linear array architectures have extremely limited routing flexibility and many designs may run out of routing resources and hence cannot be implemented. While the architecture may perform well in certain niche applications, it's utility as a general purpose MFS is very limited.
An example of a mesh architecture is shown in FIG.
2
. In the simplest mesh architecture, the FPGAs
15
a
-
15
i
are laid out in the form of a two-dimensional array with each FPGA
15
a
-
15
i
connected to its horizontal and vertical adjacent neighbors. Variations of this basic topology may be used to improve the routability of the architecture such as the torus and
8
-way mesh as shown in
FIGS. 3 and 4
. The advantages of mesh architectures are simplicity of local interconnections and easy scalability. However, by using FPGAs for interconnecting to other FPGAs, and thereby using resources of the FPGA for both interconnect and logic, the amount of logic that can be implemented within each FPGA is reduced. This leads to poor logic utilization. In addition, the connection delays between widely separated FPGAs (especially in arrays comprising large numbers of FPGAs) are large whereas those between adjacent FPGAs are small. Such irregular timing characteristics results in poor speed performance and timing problems such as setup and hold time violations due to wid

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