Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Patent
1996-10-08
1998-06-23
Niebling, John
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
438238, H01L 2100, H01L 2184
Patent
active
057704830
ABSTRACT:
A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect employs a via routed directly between the drain region of an upper level transistor to the gate of a lower level transistor so as to effect a direct coupling between the output of one transistor to the input of another. Direct coupling in this fashion affords a lower propagation delay and therefore achieves the benefit of a higher performance, faster switching circuit.
REFERENCES:
patent: 5470776 (1995-11-01), Ryou
patent: 5492851 (1996-02-01), Ryou
patent: 5610094 (1997-03-01), Ozaki et al.
Gardner Mark I.
Hause Fred N.
Kadosh Daniel
Advanced Micro Devices , Inc.
Daffer Kevin L.
Niebling John
Zarneke David A.
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