Multi-level transistor fabrication method having an inverted, up

Details Multi-level transistor fabrication method having an inverted, up Multi-level transistor fabrication method having an inverted, up

1996-10-08

1999-03-16

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438303, 438618, 438238, 438585, 438586, 438588, H01L 2100

Patent

active

058829598

ABSTRACT:
A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect achieves lower resistivity and capacitance by forming a single gate conductor which is shared by an upper level transistor and a lower level transistor. The shared gate conductor is interposed between a pair of gate dielectrics and each gate dielectric is configured between the single gate conductor and a respective substrate. Thus, the upper level transistor is inverted relative to the lower level transistor. The upper level transistor includes a substrate and junction region formed within and opening of an interlevel dielectric. The opening serves to receive the substrate material, but also to demarcate the formation of a pre-existing gate dielectric prior to substrate deposition. Sharing a single gate conductor among two transistors not only minimizes the overall routing between transistor inputs, but also is particularly attuned to inverter formation.

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