Multi-level signal lines with vertical twists

Details Multi-level signal lines with vertical twists Multi-level signal lines with vertical twists

2001-09-26

2002-08-06

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Format or disposition of elements

C365S063000

Reexamination Certificate

active

06430076

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to multi-level signal lines with vertical twists. In particular, the invention relates to multi-level bitline architectures in memory ICs.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a conventional dynamic random access memory cell
101
is shown. As shown, the memory cell comprises a cell transistor
110
and a cell capacitor
150
for storing information. A first junction
111
of the transistor is coupled to a bitline
125
, and a second junction
112
is coupled to the capacitor
150
. A gate electrode
113
of the transistor is coupled to a wordline
126
. A reference or constant voltage (V
p1
) can be coupled to a plate of the capacitor. The plate which is coupled to the reference voltage can serve as a common plate in the memory array.
Cells are arranged in rows and columns to form an array, connected by wordlines in the row direction and bitlines in the column direction. The bitlines are coupled to sense amplifiers to facilitate memory accesses. Typically, a pair of bitlines is coupled to a sense amplifier. The bitline containing the selected memory cell is referred to as the bitline or bitline true and the other is referred to as the reference bitline or bitline complement.
The bitlines can be arranged in various types of bitline architectures, such as open, folded, open-folded, diagonal, multi-level, split-level, or split-level diagonal. Multi-level or split-level bitline architectures are described in, for example, Hamada et al., A Split Level Diagonal Bitline Stack Capacitor Cell for 256 Mb DRAMs, IEDM 92-7990 and Hoenigschmid et al., A 0.21 &mgr;m2 7F Trench Cell With a Locally-Open Globally-Folded Dual Bitline For 1 Gb-4 Gb DRAM, VLSI Symp. 1998, which are herein incorporated by reference for all purposes.
FIG. 2
shows a multi-level bitline architecture with vertical twists. As shown, a bitline pair
210
comprises bitlines
211
and
212
which occupy upper and lower bitline levels
230
and
220
. The lower bitline level is referred to as M
0
and the top bitline level is referred to as M
1
. The bitlines are substantially vertically aligned with each other in the different bitline levels. Vertical twists
280
are provided to switch the levels of the bitlines from M
0
and M
1
. Memory cells
250
are coupled to the bitline segments on M
0
.
Referring to
FIG. 3
, a conventional technique for realizing a vertical twist is shown. As shown, a bitline pair
310
having first and second bitlines
311
and
312
comprises a twist
280
. The first bitline
311
includes a first segment
311
a
on M
0
and a second segment
311
b
on M
1
. The second bitline
312
includes a first segment
312
a
on M
1
and a second segment
312
b
on M
0
. The twist
280
comprises first and second contacts
340
and
350
. The first contact switches the first bitline on M
0
(segment
311
a
) to M
1
(segment
311
b
); the second contact switches the second bitline on M
1
(segment
312
a
) to M
0
(segment
312
b
). A portion of bitline segments
311
b
and
312
a
is offset on opposite sides of the bitline to avoid the contact that couples the segments of the other bitline. Such conventional realizations of the twist, however, require a larger pitch or distance between adjacent bitline pairs which results in an area penalty. This is undesirable as it results in a larger chip.
As evidenced from the foregoing discussion, it is desirable to provide an improved multi-level bitline architecture which reduces the area penalty associated with the twists.
SUMMARY OF THE INVENTION
The invention relates to multi-level signal line architectures with vertical twists. The vertical twists are used to switch the signal lines of a signal line pair from one level to another (e.g., from the first level to the second level). In one embodiment, the signal line pairs are bitline pairs. The twists are arranged to reduce coupling noise between signal line pairs. In accordance with the invention, open regions are provided in a signal line pair to accommodate an offset from a twist of an adjacent signal line pair. The open region is formed by removing a portion of the signal line in the upper level or second level and locating it on third level. The use of an open region enables smaller pitch between signal line pairs. In another embodiment, the open region accommodates two offsets, one from each of the adjacent signal line pairs.


REFERENCES:
patent: 6320780 (2001-11-01), Mueller et al.
patent: 6327170 (2001-12-01), Mueller et al.
patent: 6188598 (2002-02-01), Mueller et al.

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