Multi-level semiconductor structures having environmentally isol

Details Multi-level semiconductor structures having environmentally isol Multi-level semiconductor structures having environmentally isol

1994-01-21

1995-10-03

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Physical deformation

257698, 257750, 257777, H01L 2984, H01L 2940, H01L 2908

Patent

active

054554454

ABSTRACT:
A plurality of individual device layers having conductive regions extending therethrough are bonded together before or after one or more circuit elements have been fabricated on each one. Groups of device layers are formed by electrochemically anodizing a wafer of semiconductor material. The wafer is rendered totally porous except for a series of non-porous regions extending therethrough. The wafer is then oxidized and densified to result in a wafer having a plurality of electrically isolated extended contacts. A plurality of wafers are processed in this manner. A variety of integrated circuit devices are then formed on the surface of each wafer. The ability to separately fabricate each wafer obviates trying to incorporate various incompatible processes (required by each device type) on just one wafer surface. Once the processing of all individual wafers is completed, each wafer is bonded to another at appropriate areas, with the extending contact aligned to electrically interconnect each device layer. The wafers are then diced to provide a plurality of multi-level integrated circuit structures.

REFERENCES:
patent: 4786954 (1988-11-01), Morie et al.
patent: 4972248 (1990-11-01), Kornreich et al.
patent: 5266833 (1993-11-01), Capps
Journal of the Electrochemical Society, vol. 139, No. 12, by C. Oules, A. Halimaoui, J. L. Fegolini, A Perio and G. Bomchil, Dec., 1992, pp. 3595-3598.

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