Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2002-12-20
2004-11-16
Zarneke, David A. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S767000, C438S612000, C438S597000
Reexamination Certificate
active
06818996
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the design of flip-chip packages used in the manufacture of integrated circuits. More specifically, but without limitation thereto, the present invention relates to metal redistribution layer traces in an integrated circuit die.
2. Description of the Prior Art
An important issue in microelectronic packaging is reliability. Technologies for microelectronic packaging are developed not only to manufacture microelectronic packages at low cost, but also to ensure that the performance of the microelectronic packages will not deteriorate over their service life. A critical factor in determining the service life of an integrated circuit is the redistribution of current through the metal redistribution layer of the integrated circuit die. The metal redistribution layer is a conductive layer formed on a surface of the die in which traces are formed that connect various signals and power between the die and I/O pads formed on the surface of the die. The I/O pads connect the signals between the traces and the package substrate through solder bumps. In certain areas of the solder bumps near the junctions of the traces and the I/O pads, the current density reaches a maximum that may shorten the useful life of the integrated circuit. The peaking of the current density at the junctions of the traces and the I/O pads and in the solder bumps is generally referred to as current crowding. It has been discovered that current crowding results in the deterioration of not only the trace junctions, which decreases the wafer level reliability, but also the solder bumps, which decreases the package level reliability.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a multi-level redistribution layer trace reduces current crowding in solder bumps of an integrated circuit package. In one embodiment, a multi-level redistribution layer trace for an integrated circuit die includes a redistribution layer trace formed on the integrated circuit die in each of a plurality of electrically conductive layers and an I/O pad formed at a termination of the redistribution layer trace so that the I/O pad extends through each of the plurality of electrically conductive layers to form an electrical junction between the termination of the redistribution layer trace and the I/O pad in each of the plurality of electrically conductive layers.
In another aspect of the present invention, a method of making a multi-level redistribution layer trace of an integrated circuit die includes the steps of forming a redistribution layer trace on the integrated circuit die in each of a plurality of electrically conductive layers, and forming an I/O pad at a termination of the redistribution layer trace so that the I/O pad extends through each of the plurality of electrically conductive layers to form an electrical junction between the termination of the redistribution layer trace and the I/O pad in each of the plurality of electrically conductive layers.
In a further aspect of the present invention, a multi-level redistribution layer trace of an integrated circuit die includes a redistribution layer trace formed on the integrated circuit die in one or more electrically conductive layers, and a slot formed in the redistribution layer trace to divide the current flow horizontally at an electrical junction between a termination of the redistribution layer trace and an I/O pad.
In yet another aspect of the present invention, a method of making a multi-level redistribution layer trace of an integrated circuit die includes the steps of forming a redistribution layer trace on the integrated circuit die in one or more electrically conductive layers, and forming a slot in the redistribution layer trace to divide the current flow horizontally at an electrical junction between a termination of the redistribution layer trace and an I/O pad.
REFERENCES:
patent: 3239719 (1966-03-01), Shower
patent: 3517278 (1970-06-01), Hager
patent: 4603345 (1986-07-01), Lee et al.
patent: 4654692 (1987-03-01), Sakurai et al.
patent: 4825284 (1989-04-01), Soga et al.
patent: 4893172 (1990-01-01), Matsumoto
patent: 5239448 (1993-08-01), Perkins
patent: 5289036 (1994-02-01), Nishimoto
patent: 5382831 (1995-01-01), Atakov et al.
patent: 5461260 (1995-10-01), Varker et al.
patent: 5689139 (1997-11-01), Bui et al.
patent: 5847936 (1998-12-01), Forehand
patent: 5969421 (1999-10-01), Smooha
patent: 6169326 (2001-01-01), Jun
patent: 6417572 (2002-07-01), Chidambarrao et al.
patent: 6522021 (2003-02-01), Sakihama et al.
Mertol Atila
Pekin Senol
Fitch Even Tabin & Flannery
LSI Logic Corporation
Zarneke David A.
LandOfFree
Multi-level redistribution layer traces for reducing current... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multi-level redistribution layer traces for reducing current..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-level redistribution layer traces for reducing current... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3305665