Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
1997-03-27
2002-04-30
Santamauro, Jon (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S062000, C326S063000, C326S068000, C326S080000
Reexamination Certificate
active
06380762
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the area of integrated circuit devices, and more specifically to such devices capable of operating at a variety of different voltage levels.
BACKGROUND
Integrated circuit (IC) devices are usually supplied with one operating voltage that is common to all of the individual circuits within the device. In the past, most IC devices were designed to operate at 5.0 volts. Yet, there has always been a desire to operate IC devices at lower voltages (e.g., 3.3 volts) due to a substantially lower power dissipation as compared with the 5.0 volt operating voltage. Nevertheless, operating at lower operating voltages resulted in slower performance of ICs, despite lower power consumption. Therefore, there had previously been a design trade-off between lower power dissipation or higher performance.
As technology has advanced, IC designers are no longer restricted by the past speed constraints associated with using a lower voltage to operate ICs. At present, some of the most popular IC devices operate at 3.3 volts. However, many manufacturers continue to use 5.0 volts as the operating voltage for their ICs. Consequently, it is desirable for designers to configure ICs such that they are capable of operating at either 3.3 or 5.0 volts (or other operating voltages).
Current IC devices incorporate metal mask options or fuses, which are used to select between different operating voltages within each circuit of an IC device. One problem with IC devices that incorporate such means for selecting different operating voltages is that once a metal mask option is selected (or a fuse blown) there is no way to reconfigure the device to operate at another operating voltage. For example, once the 5.0 volt option is selected, there is no way to reconfigure a circuit within the IC device to operate at 3.3 volts. In addition, each internal circuit requires its own fuse or metal mask option, causing the verification of the IC device before manufacture to become a complex process.
In some IC circuits, such as output buffers, designing the circuit with multiple operating voltage capabilities can lead to diminished performance or noise problems. For example, output buffers designed for higher operating voltages (e.g., 5.0 volts) are too slow when operated at a lower voltages (e.g., 3.3 volts). In other words, more current is needed to drive the output buffer at the high operating voltage speeds than can be provided by the low voltage design. However, output buffers designed for use with low operating voltages generate unacceptable amounts of ground bounce (or noise) when operated at higher voltages. The ground bounce is caused by current generated by switching to the high voltage signal, which is greater than needed to drive the output buffer at the lower operating voltage. Therefore, means for controlling the speed and ground bounce of an output buffer that is capable of operating at different voltages is desired.
SUMMARY OF THE INVENTION
An integrated circuit device includes an input circuit; logic circuitry coupled to the input circuit; an output circuit coupled to the logic circuitry; and a select circuit coupled to the input circuit, output circuit and logic circuitry. The select circuit generates a select signal that causes the input circuit, output circuit and logic circuit to operate according to a first state or a second state. In one embodiment, the first and second states may correspond to different operating voltages.
According to a further embodiment, the select circuit includes a first switch circuit that generates a first signal which corresponds to the first state and a second switch circuit that generates a second signal that corresponds to the second state. In addition, the select circuit may include a logic circuit that produces the select signal by selecting either the first signal or the second signal.
According to another embodiment, the output buffer includes a first driving circuit, a second driving circuit, and an output pad coupled to the first driving circuit and the second driving circuit. The output buffer is configured to receive a data signal, a control signal, and the select signal. The select signal selects output buffer operation at the first state or the second state. The output buffer is also configured to maintain an approximately constant slew rate while operating in either the first or second state.
REFERENCES:
patent: 4853560 (1989-08-01), Iwamura et al.
patent: 5099453 (1992-03-01), Steele
patent: 5426616 (1995-06-01), Kajigaya et al.
patent: 5532618 (1996-07-01), Hardee et al.
patent: 5747890 (1998-05-01), Yin
Gibbs Gary A.
Pancholy Ashish
Cypress Semiconductor Corporation
Paik Steven S.
Santamauro Jon
Wagner, Murabiot & Hao LLP
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