Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-01-26
2003-09-23
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06625781
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a model for power consumption for electrical circuits, specifically a CMOS macrocell.
2. Description of the Related Art
The power consumption of a macrocell is calculated based on the switching activity of the individual boundary pins. The power consumption of the macrocell is calculated as the sum of the product between switching activity and power coefficient for the individual pins. The individual power coefficient captures technology-specific data and environment conditions, such as voltage, temperature, load capacitance for output pins. The individual power coefficient captures technology-specific data including the slewrate for input pins. With this technique, the power consumption of a macrocell with N pins can be modeled with N power coefficients. The only data required is provided by observing or estimating the switching activity on each net of the design.
Characterization of the power coefficients based on switching activity alone does not support accurate power modeling, even for small cells. The power coefficient of the output pin captures the effect of load capacitance. The respective power coefficients for input pins must capture the effect of the respective slewrates. However, a switching signal on an input pin will have only a noticeable power consumption effect, if the output is switching which leads to incorrect results. The correct this inaccuracy, the invention considers the slewrate on the input pins when calculating the power coefficient for the output pins.
For small cells the load effects are much more dominant on power consumption than the slewrate effects. Therefore, modeling with power coefficients only for output pins is an improvement for small cells. But for larger cells, a greater percentage of the power is consumed internally. One way of accounting for internal power for large and small cells is to observe both primary output pins and internal output pins. The difficulty is to decide which internal pins are most relevant for power consumption. Observing all internal pins would actually defeat the purpose of macromodeling because one would have merely a collection of models for the constituent components of the macrocell. A collection of models for the constituent components of a macrocell provides an adequate model of certain cells, such as a flipflop but not for the majority of macrocells.
Considering state dependency improves the accuracy of the power pin model. The switching activity for each pin as well as the state of other pins is determined. Instead of one power coefficient per pin, the model uses multiple power coefficients per pin. The model uses the relevant states on other pins to determine the number of power coefficients required for each pin. State-dependency provides a power pin model applicable to all cells, not only flip flops.
For pins with state dependency, the number of rising edges is not necessarily equal to the number of falling edges. Therefore, for pins with state dependency, it is necessary to determine which signals on which pins are rising and which signals are falling. While the total number of rising and falling edges on a signal is the same in a repeatable scenario, particular rising and falling edges may occur in different logic states of the circuit. For example, all rising edges could occur while the circuit is in state A whereas all falling edges occur while the circuit is in state B. The circuit may have different power consumption for rising edge during state A, falling edge during state A, rising edge during state B and falling edge during state B. Therefore, we need to distinguish between rising and falling edges during each state.
The number of permutations of rising and falling pins increases with the size of the cell. The relationship increases exponentially, N pins have 2N possible states. The present invention collapses some states in order to reduce the complexity. Prior art approaches may combine certain states if the power consumption between those states is similar. However, exhaustive characterization of all states is needed before reducing the number of states. Simultaneously switching pins also increases the number of power coefficients.
But collapsing states requires starting with a large number of permutations. When characterizing the power consumption of all possible states exhaustively, certain states may be found to have negligible power consumption. Those states can be reduced from the power model. Again, exhaustive characterization is required.
The dependency between slewrate of the input pin and the load capacitance of the outpin cannot be accurately modeled by a one-dimensional function for slewrate attached to the input and one-dimensional function for the load capacitance. A need exists for a model with two dimensions, or more.
SUMMARY OF THE INVENTION
The invention utilizes the linear complexity of orthogonal vectors to reduce the number of equations (or variables) to be solved. The present invention constructs a power model of a set of combinations of states without considering irrelevant combinations. The invention distinguishes between the switching direction on the input and the output pin. The invention considers state-dependency as a function of power consumed and depending on the paths through internal nodes. The model considers switching input pins that do not cause the output pin to switch to overcome inaccuracies caused by combining the power pin model with the state and arc power model with state. The model considers switching input pins that cause the output pin to switch. For cells in which the slewrate propagation effect from input to output is negligible, the invention uses a model of 2 power pins with state. The invention also determines the validity of this model. The present invention also models a power arc from one input pin to multiple output pins.
The foregoing is a summary and this contains, by necessity, simplifications, generalizations and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting.
REFERENCES:
patent: 4698760 (1987-10-01), Lembach et al.
patent: 5598344 (1997-01-01), Dangelo et al.
Balakrishnan Arun
Lakshminarayana Ganesh
Raghunathan Anand
Roethig Wolfgang
Bowers Brandon
Garbowski Leigh M.
NEC Electronics Inc.
Skjerven Morrill LLP
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